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MAX3109ETJ+

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Maxim Integrated UART, TQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX3109ETJ+

Maxim Integrated · UART · TQFN-32-EP(5x5)

MAX3109ETJ+ from Maxim Integrated, in a TQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RST input Active-low reset input that forces all UARTs into hardware reset and enables low-power shutdown when driven low, and it switches off the internal V18 LDO even if LDOEN is high.
2 MISO/SDA bidirectional Serial-data pin that acts as SPI MISO output when SPI/I2C is high and as the I2C SDA data line when SPI/I2C is low, and it is high impedance when RST is low or V18 is powered off.
3 SCLK/SCL input Serial-clock input that accepts SPI SCLK up to 26MHz when SPI/I2C is high and I2C SCL up to 1MHz in fast mode plus when SPI/I2C is low.
4 GPIO7 bidirectional User-programmable general-purpose I/O that can be push-pull or open drain and has a weak pulldown to DGND when configured as an input.
5 CS/A0 input Active-low SPI chip select when SPI/I2C is high, or the A0 I2C address programming input when SPI/I2C is low, which must be connected to DGND, VL, SCL, or SDA in I2C mode.
6 MOSI/A1 input SPI master-output slave-input when SPI/I2C is high, or the A1 I2C address programming input when SPI/I2C is low, which must be connected to DGND, VL, SCL, or SDA in I2C mode.
7 IRQ output Active-low interrupt open-drain output that is asserted when an interrupt is pending and is high impedance when RST is driven low.
8 VL power_in Digital interface supply that powers the logic-level translators for RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C, and should be bypassed with a 0.1µF ceramic capacitor to DGND.
9 SPI/I2C input Interface selector where driving the pin high enables SPI and driving it low enables I2C.
10 DGND power_in Digital ground reference for the device.
11 GPIO0 bidirectional User-programmable general-purpose I/O with a weak pulldown to DGND when input, and it outputs the reference clock when bit 7 of the TxSynch register is set high.
12 GPIO4 bidirectional User-programmable general-purpose I/O with a weak pulldown to DGND when input, and it outputs the reference clock when bit 7 of the TxSynch register is set high.
13 GPIO1 bidirectional User-programmable general-purpose I/O with a weak pulldown to DGND when input, and it outputs the TIMER signal when bit 7 of the TIMER2 register is set high.
14 GPIO5 bidirectional User-programmable general-purpose I/O with a weak pulldown to DGND when input, and it outputs the TIMER signal when bit 7 of the TIMER2 register is set high.
15 CTS0 input Active-low clear-to-send flow-control status input for UART0.
16 CTS1 input Active-low clear-to-send flow-control status input for UART1.
17 TX1 output Serial transmit data output for UART1 that is logic-high when RST is low or when the externally supplied V18 is not powered.
18 TX0 output Serial transmit data output for UART0 that is logic-high when RST is low or when the externally supplied V18 is not powered.
19 RX0 input Serial receive data input for UART0 with an internal weak pullup resistor to VEXT.
20 RX1 input Serial receive data input for UART1 with an internal weak pullup resistor to VEXT.
21 RTS0 output Active-low request-to-send output for UART0 that can be set high or low through the LCR register and is logic-high when RST is low or V18 is not powered.
22 RTS1 output Active-low request-to-send output for UART1 that can be set high or low through the LCR register and is logic-high when RST is low or V18 is not powered.
23 GPIO2 bidirectional User-programmable general-purpose I/O that can be push-pull or open drain and has a weak pulldown to DGND when configured as an input.
24 GPIO3 bidirectional User-programmable general-purpose I/O that can be push-pull or open drain and has a weak pulldown to DGND when configured as an input.
25 VEXT power_in Transceiver interface supply that powers the logic-level translators for RX_, TX_, RTS_, CTS_, and GPIO_, and should be bypassed with a 0.1µF ceramic capacitor to DGND.
26 XIN input Crystal or clock input where a crystal connects between XIN and XOUT, or an external single-ended clock is driven.
27 XOUT passive Crystal output that connects to the other end of the crystal from XIN, and must be left unconnected when an external clock source is used.
28 GPIO6 bidirectional User-programmable general-purpose I/O that can be push-pull or open drain and has a weak pulldown to DGND when configured as an input.
29 AGND power_in Analog ground reference for the device that the exposed pad must be connected to.
30 LDOEN input LDO enable input where driving it high enables the internal 1.8V LDO and driving it low disables it, requiring an external V18 supply.
31 V18 power_in Internal 1.8V LDO output and 1.8V power-supply input that should be bypassed with a 1µF ceramic capacitor to DGND.
32 VCC power_in Analog supply that powers the PLL and internal LDO, specified at 1.71V to 3.6V with the PLL bypassed and 2.35V to 3.6V with the PLL enabled, and should be bypassed with a 0.1µF ceramic capacitor to AGND.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package TQFN-32-EP(5x5)
Category Interface ICs
Pins 33

CAD (KiCad official)

  • Symbol: MAX3109ETJ+
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: TQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: max3109etj-etched.step / max3109etj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max3109etj.step / max3109etj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (66 pp, sha256 2a6e460cb0dda736, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF