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MAX22246FAWA+

Analog Devices Inc./Maxim Integrated · Digital Isolators · SOIC-8

MAX22246FAWA+ from Analog Devices Inc./Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Power supply input for Side A (1.71V to 5.5V relative to GNDA); bypass to GNDA with a 0.1µF ceramic capacitor as close to the pin as possible.
2 OUT1 output Logic output 1 on Side A (MAX22246: channel 1 transfers data from Side B IN1 to Side A OUT1), push-pull output; default-low on the F version.
3 IN2 input Logic input 2 on Side A, passed to OUT2 on Side B, with 5µA typical internal pulldown current on the F version.
4 GNDA power_in Ground reference for Side A.
5 GNDB power_in Ground reference for Side B.
6 OUT2 output Logic output 2 on Side B, push-pull output; default-low on the F version.
7 IN1 input Logic input 1 on Side B, passed to OUT1 on Side A, with 5µA typical internal pulldown current on the F version.
8 VDDB power_in Power supply input for Side B (1.71V to 5.5V relative to GNDB); bypass to GNDB with a 0.1µF ceramic capacitor as close to the pin as possible.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc./Maxim Integrated
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDA VDDA 1.71 5.5 V Relative to GNDA 3
Supply Voltage VDDB VDDB 1.71 5.5 V Relative to GNDB 3
Undervoltage-Lockout Threshold VUVLO_ 1.5 1.6 1.66 V VDD_ rising 3
Undervoltage-Lockout Threshold Hysteresis VUVLO_HYST 45 mV 3
Input Low Voltage VIL 0.8 V 2.25V ≤ VDD_ ≤ 5.5V 4
Input Low Voltage VIL 0.7 V 1.71V ≤ VDD_ < 2.25V 4
Input Hysteresis VHYS 80 mV MAX2224_C/F 4
Input Pulldown Current IPD 1.5 5 10 µA MAX2224_E/F 4
Input Capacitance CIN 2 pF fSW = 1MHz 4
Output Voltage Low VOL 0.4 V IOUT = 4mA sink 4
Common-Mode Transient Immunity CMTI 50 kV/µs IN_ = GND_ or VDD_ (Note 5) 4
Maximum Data Rate DRMAX 200 Mbps 2.25V ≤ VDD_ ≤ 5.5V 4
Maximum Data Rate DRMAX 150 Mbps 1.71V ≤ VDD_ < 2.25V 4
Minimum Pulse Width PWMIN 5 ns 2.25V ≤ VDD_ ≤ 5.5V 4
Minimum Pulse Width PWMIN 6.67 ns 1.71V ≤ VDD_ < 2.25V 4
Propagation Delay tPLH tPLH 4.4 6.2 9.5 ns IN_ to OUT_, CL = 15pF, 4.5V ≤ VDD_ ≤ 5.5V 4
Propagation Delay tPLH tPLH 4.8 7 11.2 ns IN_ to OUT_, CL = 15pF, 3.0V ≤ VDD_ ≤ 3.6V 4
Propagation Delay tPLH tPLH 5.3 8.3 14.7 ns IN_ to OUT_, CL = 15pF, 2.25V ≤ VDD_ ≤ 2.75V 4
Propagation Delay tPLH tPLH 7.1 12.3 22.1 ns IN_ to OUT_, CL = 15pF, 1.71V ≤ VDD_ ≤ 1.89V 4
Propagation Delay tPHL tPHL 4.6 6.5 9.9 ns IN_ to OUT_, CL = 15pF, 4.5V ≤ VDD_ ≤ 5.5V 4
Propagation Delay tPHL tPHL 5 7.3 11.6 ns IN_ to OUT_, CL = 15pF, 3.0V ≤ VDD_ ≤ 3.6V 4
Propagation Delay tPHL tPHL 5.4 8.5 14.9 ns IN_ to OUT_, CL = 15pF, 2.25V ≤ VDD_ ≤ 2.75V 4
Propagation Delay tPHL tPHL 7.2 12.1 21.8 ns IN_ to OUT_, CL = 15pF, 1.71V ≤ VDD_ ≤ 1.89V 4
Pulse Width Distortion PWD 0.4 2 ns /tPLH - tPHL/, 4.5V ≤ VDD_ ≤ 5.5V 4
Pulse Width Distortion PWD 0.3 2 ns /tPLH - tPHL/, 2.25V ≤ VDD_ ≤ 2.75V 4
Pulse Width Distortion PWD 0 2 ns /tPLH - tPHL/, 1.71V ≤ VDD_ ≤ 1.89V 5
Channel-to-Channel Skew (Same Direction) tSCSLH 2 ns 1.71V ≤ VDD_ ≤ 5.5V 5
Channel-to-Channel Skew (Opposite Direction) tSCOLH 2 ns 1.71V ≤ VDD_ ≤ 5.5V 5
Side A Supply Current IDDA 0.46 0.84 mA 500kHz square wave, CL = 0pF, VDDA = 5V 3
Side A Supply Current IDDA 0.45 0.83 mA 500kHz square wave, CL = 0pF, VDDA = 3.3V 3
Side A Supply Current IDDA 0.44 0.83 mA 500kHz square wave, CL = 0pF, VDDA = 2.5V 3
Side A Supply Current IDDA 0.44 0.74 mA 500kHz square wave, CL = 0pF, VDDA = 1.8V 3
Side A Supply Current IDDA 2.65 3.5 mA 50MHz square wave, CL = 0pF, VDDA = 5V 3
Side A Supply Current IDDA 2.18 2.95 mA 50MHz square wave, CL = 0pF, VDDA = 3.3V 3
Side A Supply Current IDDA 1.98 2.72 mA 50MHz square wave, CL = 0pF, VDDA = 2.5V 3
Side A Supply Current IDDA 1.8 2.4 mA 50MHz square wave, CL = 0pF, VDDA = 1.8V 3
Side B Supply Current IDDB 0.46 0.84 mA 500kHz square wave, CL = 0pF, VDDB = 5V 3
Side B Supply Current IDDB 0.45 0.83 mA 500kHz square wave, CL = 0pF, VDDB = 3.3V 3
Side B Supply Current IDDB 0.44 0.83 mA 500kHz square wave, CL = 0pF, VDDB = 2.5V 3
Side B Supply Current IDDB 0.44 0.74 mA 500kHz square wave, CL = 0pF, VDDB = 1.8V 3
Side B Supply Current IDDB 2.65 3.5 mA 50MHz square wave, CL = 0pF, VDDB = 5V 3
Side B Supply Current IDDB 2.18 2.95 mA 50MHz square wave, CL = 0pF, VDDB = 3.3V 3
Side B Supply Current IDDB 1.98 2.72 mA 50MHz square wave, CL = 0pF, VDDB = 2.5V 4
Side B Supply Current IDDB 1.8 2.4 mA 50MHz square wave, CL = 0pF, VDDB = 1.8V 4
Peak Eye Diagram Jitter tJIT(PK) 100 ps 200Mbps 5
Clock Jitter RMS tJCLK(RMS) 7.5 ps 500kHz clock input, rising/falling edges 5
VDD to GND VDDA/VDDB -0.3 6 V VDDA to GNDA, VDDB to GNDB 2
IN_ to GND IN_ -0.3 6 V Side A to GNDA, Side B to GNDB 2
Short-Circuit Continuous Current -30 30 mA OUT_ to GND_ (printed ±30mA) 2
Continuous Power Dissipation PD 908.1 mW TA = +70°C, Wide SOIC, derate 11.35mW/°C above +70°C 2
Operating Temperature Range TA -40 125 °C 2
Maximum Junction Temperature TJ 150 °C 2
Storage Temperature Range TSTG -60 150 °C 2
Lead Temperature (soldering, 10s) 300 °C 10s 2
Junction-to-Ambient Thermal Resistance θJA 88.1 °C/W 8 Wide SOIC, four-layer board, JESD51-7 2
Junction-to-Case Thermal Resistance θJC 42.4 °C/W 8 Wide SOIC, four-layer board, JESD51-7 2
ESD Human Body Model -3 3 kV All pins, TA = +25°C (printed ±3) 7
ESD IEC 61000-4-2 Contact -7 7 kV GNDB to GNDA, TA = +25°C (printed ±7) 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pet The MAX22245/MAX22246 are certified to DIN VDE V 0884-11: 2017-1. Reinforced Insulation, Maximum Transient Isolation Voltage 7000VPK, Maximum Repetitive Peak Isolation Voltage 1200VPK. 9

CAD (KiCad official)

  • Symbol: MAX22246FAWA+
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: max22246fawa-etched.step / max22246fawa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max22246fawa.step / max22246fawa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc./Maxim Integrated datasheet (22 pp, sha256 b87baf43c106104d, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF