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MAX22246CAWA+

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Analog Devices Inc./Maxim Integrated Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MAX22246CAWA+

Analog Devices Inc./Maxim Integrated · Digital Isolators · SOIC-8

MAX22246CAWA+ from Analog Devices Inc./Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Power supply input for Side A, specified 1.71V to 5.5V relative to GNDA; bypass VDDA to GNDA with a 0.1µF ceramic capacitor as close as possible to the pin.
2 OUT1 output Logic output 1 on Side A, carrying the channel 1 data received from IN1 on Side B for the MAX22246.
3 IN2 input Logic input 2 on Side A, referenced to GNDA and powered from VDDA.
4 GNDA power_in Ground reference for Side A; VDDA is referenced to this pin.
5 GNDB power_in Ground reference for Side B; VDDB is referenced to this pin.
6 OUT2 output Logic output 2 on Side B, carrying the channel 2 data received from IN2 on Side A for the MAX22246.
7 IN1 input Logic input 1 on Side B, referenced to GNDB and powered from VDDB.
8 VDDB power_in Power supply input for Side B, specified 1.71V to 5.5V relative to GNDB; bypass VDDB to GNDB with a 0.1µF ceramic capacitor as close as possible to the pin.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc./Maxim Integrated
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDA Relative to GNDA VDDA 1.71 5.5 V VDDA Relative to GNDA 3
Supply Voltage VDDB Relative to GNDB VDDB 1.71 5.5 V VDDB Relative to GNDB 3
Undervoltage-Lockout Threshold VUVLO_ 1.5 1.6 1.66 V VUVLO_ VDD_ rising 3
Input Low Voltage VIL 0.8 V 2.25V ≤ VDD_ ≤ 5.5V 4
Input Low Voltage VIL 0.7 V 1.71V ≤ VDD_ < 2.25V 4
Input Pullup Current IPU -10 -5 -1.5 µA MAX2224_B/C 4
Output Voltage Low VOL 0.4 V IOUT = 4mA sink 4
Side A Supply Current IDDA 0.46 0.84 mA 500kHz square wave, CL = 0pF; VDDA = 5V 3
Side A Supply Current IDDA 0.45 0.83 mA 500kHz square wave, CL = 0pF; VDDA = 3.3V 3
Side A Supply Current IDDA 0.44 0.83 mA 500kHz square wave, CL = 0pF; VDDA = 2.5V 3
Side A Supply Current IDDA 0.44 0.74 mA 500kHz square wave, CL = 0pF; VDDA = 1.8V 3
Side A Supply Current IDDA 2.65 3.5 mA 50MHz square wave, CL = 0pF; VDDA = 5V 3
Side A Supply Current IDDA 2.18 2.95 mA 50MHz square wave, CL = 0pF; VDDA = 3.3V 3
Side A Supply Current IDDA 1.98 2.72 mA 50MHz square wave, CL = 0pF; VDDA = 2.5V 3
Side A Supply Current IDDA 1.8 2.4 mA 50MHz square wave, CL = 0pF; VDDA = 1.8V 3
Side B Supply Current IDDB 0.46 0.84 mA 500kHz square wave, CL = 0pF; VDDB = 5V 3
Side B Supply Current IDDB 0.45 0.83 mA 500kHz square wave, CL = 0pF; VDDB = 3.3V 3
Side B Supply Current IDDB 0.44 0.83 mA 500kHz square wave, CL = 0pF; VDDB = 2.5V 3
Side B Supply Current IDDB 0.44 0.74 mA 500kHz square wave, CL = 0pF; VDDB = 1.8V 3
Side B Supply Current IDDB 2.65 3.5 mA 50MHz square wave, CL = 0pF; VDDB = 5V 3
Side B Supply Current IDDB 2.18 2.95 mA 50MHz square wave, CL = 0pF; VDDB = 3.3V 3
Side B Supply Current IDDB 1.98 2.72 mA 50MHz square wave, CL = 0pF; VDDB = 2.5V 4
Side B Supply Current IDDB 1.8 2.4 mA 50MHz square wave, CL = 0pF; VDDB = 1.8V 4
Maximum Data Rate DRMAX 200 Mbps 2.25V ≤ VDD_ ≤ 5.5V 4
Maximum Data Rate DRMAX 150 Mbps 1.71V ≤ VDD_ < 2.25V 4
Minimum Pulse Width PWMIN 5 ns 2.25V ≤ VDD_ ≤ 5.5V 4
Minimum Pulse Width PWMIN 6.67 ns 1.71V ≤ VDD_ < 2.25V 4
Propagation Delay tPLH tPLH 4.4 6.2 9.5 ns IN_ to OUT_, CL = 15pF, 4.5V ≤ VDD_ ≤ 5.5V 4
Propagation Delay tPLH tPLH 4.8 7 11.2 ns IN_ to OUT_, CL = 15pF, 3.0V ≤ VDD_ ≤ 3.6V 4
Propagation Delay tPLH tPLH 5.3 8.3 14.7 ns IN_ to OUT_, CL = 15pF, 2.25V ≤ VDD_ ≤ 2.75V 4
Propagation Delay tPLH tPLH 7.1 12.3 22.1 ns IN_ to OUT_, CL = 15pF, 1.71V ≤ VDD_ ≤ 1.89V 4
Propagation Delay tPHL tPHL 4.6 6.5 9.9 ns IN_ to OUT_, CL = 15pF, 4.5V ≤ VDD_ ≤ 5.5V 4
Propagation Delay tPHL tPHL 5 7.3 11.6 ns IN_ to OUT_, CL = 15pF, 3.0V ≤ VDD_ ≤ 3.6V 4
Propagation Delay tPHL tPHL 5.4 8.5 14.9 ns IN_ to OUT_, CL = 15pF, 2.25V ≤ VDD_ ≤ 2.75V 4
Propagation Delay tPHL tPHL 7.2 12.1 21.8 ns IN_ to OUT_, CL = 15pF, 1.71V ≤ VDD_ ≤ 1.89V 4
Pulse Width Distortion PWD 0.4 2 ns /tPLH - tPHL/, 4.5V ≤ VDD_ ≤ 5.5V 4
Pulse Width Distortion PWD 0 2 ns /tPLH - tPHL/, 1.71V ≤ VDD_ ≤ 1.89V 5
Rise Time tR 0.8 ns CL = 5pF, 4.5V ≤ VDD_ ≤ 5.5V 5
Rise Time tR 1.1 ns CL = 5pF, 3.0V ≤ VDD_ ≤ 3.6V 5
Rise Time tR 1.5 ns CL = 5pF, 2.25V ≤ VDD_ ≤ 2.75V 5
Rise Time tR 2.4 ns CL = 5pF, 1.71V ≤ VDD_ ≤ 1.89V 5
Fall Time tF 1 ns CL = 5pF, 4.5V ≤ VDD_ ≤ 5.5V 5
Fall Time tF 1.4 ns CL = 5pF, 3.0V ≤ VDD_ ≤ 3.6V 5
Fall Time tF 1.9 ns CL = 5pF, 2.25V ≤ VDD_ ≤ 2.75V 5
Fall Time tF 3 ns CL = 5pF, 1.71V ≤ VDD_ ≤ 1.89V 5
Supply Voltage VDDA to GNDA (absolute maximum) VDDA -0.3 6 V 2
Supply Voltage VDDB to GNDB (absolute maximum) VDDB -0.3 6 V 2
IN_ on Side A to GNDA IN_ -0.3 6 V IN_ on Side A to GNDA 2
IN_ on Side B to GNDB IN_ -0.3 6 V IN_ on Side B to GNDB 2
OUT_ on Side A to GNDA OUT_ -0.3 V OUT_ on Side A to GNDA; upper limit printed as VDDA + 0.3V 2
OUT_ on Side B to GNDB OUT_ -0.3 V OUT_ on Side B to GNDB; upper limit printed as VDDB + 0.3V 2
Continuous Power Dissipation 908.1 mW TA = +70°C, Wide SOIC derate 11.35mW/°C above +70°C 2
Operating Temperature Range TA -40 125 °C 2
Junction-to-Ambient Thermal Resistance θJA 88.1 °C/W Four-layer board, JESD51-7 2
Safety Current on Any Pin IS 300 mA TJ = 150°C, TA = 25°C 16
Common-Mode Transient Immunity CMTI 50 kV/µs IN_ = GND_ or VDD_ (Note 5) 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pet The MAX22245/MAX22246 are certified to DIN VDE V 0884-11: 2017-1. Reinforced Insulation, Maximum Transient Isolation Voltage 7000VPK, Maximum Repetitive Peak Isolation Voltage 1200VPK. 9

CAD (KiCad official)

  • Symbol: MAX22246CAWA+
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: max22246cawa-etched.step / max22246cawa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max22246cawa.step / max22246cawa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc./Maxim Integrated datasheet (22 pp, sha256 b87baf43c106104d, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF