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MAX1978ETM+T

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Analog Devices Inc Maxim Integrated Battery Management, TQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MAX1978ETM+T

Analog Devices Inc Maxim Integrated · Battery Management · TQFN-48-EP(7x7)

MAX1978ETM+T from Analog Devices Inc Maxim Integrated, in a TQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OS2 input Output Sense 2 senses one side of the differential TEC voltage and is a sense point, not a power output.
2 N.C. unconnected Not internally connected.
3 PGND2 power_in Power Ground 2 is the internal synchronous rectifier ground connection; connect all PGND pins together at the power ground plane.
4 LX2 output Inductor 2 connection; connect all LX2 pins together and connect LX2 to LX1 when using the MAX1979.
5 PGND2 power_in Power Ground 2 is the internal synchronous rectifier ground connection; connect all PGND pins together at the power ground plane.
6 LX2 output Inductor 2 connection; connect all LX2 pins together and connect LX2 to LX1 when using the MAX1979.
7 PVDD2 power_in Power 2 input must be the same voltage as VDD; bypass to PGND2 with a 10µF ceramic capacitor.
8 N.C. unconnected Not internally connected.
9 LX2 output Inductor 2 connection; connect all LX2 pins together and connect LX2 to LX1 when using the MAX1979.
10 PVDD2 power_in Power 2 input must be the same voltage as VDD; bypass to PGND2 with a 10µF ceramic capacitor.
11 SHDN input Active-low shutdown control input.
12 OT output Over-temperature alarm open-drain output pulls low if temperature feedback rises 20mV (typically +1.5°C) above the set-point voltage.
13 UT output Under-temperature alarm open-drain output pulls low if temperature feedback falls 20mV (typically +1.5°C) below the set-point voltage.
14 INTOUT output Integrator amplifier output, normally connected to CTLI.
15 INT- input Integrator amplifier inverting input, normally connected to DIFOUT through the thermal-compensation network.
16 GND power_in Analog ground; connect all GND pins to the analog ground plane.
17 DIFOUT output Chopper-stabilized instrumentation amplifier output with differential gain of 50 × (FB+ - FB-).
18 FB- input Chopper-stabilized instrumentation amplifier inverting input, connected to the thermistor bridge.
19 FB+ input Chopper-stabilized instrumentation amplifier noninverting input, connected to the thermistor bridge.
20 BFB- output Chopper-stabilized buffered FB- output used to monitor the thermistor bridge voltage.
21 BFB+ output Chopper-stabilized buffered FB+ output used to monitor the thermistor bridge voltage.
22 AIN+ input Undedicated chopper-stabilized amplifier noninverting input.
23 AIN- input Undedicated chopper-stabilized amplifier inverting input.
24 AOUT output Undedicated chopper-stabilized amplifier output.
25 GND power_in Analog ground; connect all GND pins to the analog ground plane.
26 GND power_in Analog ground; connect all GND pins to the analog ground plane.
27 PVDD1 power_in Power 1 input must be the same voltage as VDD; bypass to PGND1 with a 10µF ceramic capacitor.
28 LX1 output Inductor 1 connection; connect all LX1 pins together and connect LX1 to LX2 when using the MAX1979.
29 N.C. unconnected Not internally connected.
30 PVDD1 power_in Power 1 input must be the same voltage as VDD; bypass to PGND1 with a 10µF ceramic capacitor.
31 LX1 output Inductor 1 connection; connect all LX1 pins together and connect LX1 to LX2 when using the MAX1979.
32 PGND1 power_in Power Ground 1 is the internal synchronous-rectifier ground connection; connect all PGND pins together at the power ground plane.
33 LX1 output Inductor 1 connection; connect all LX1 pins together and connect LX1 to LX2 when using the MAX1979.
34 PGND1 power_in Power Ground 1 is the internal synchronous-rectifier ground connection; connect all PGND pins together at the power ground plane.
35 N.C. unconnected Not internally connected.
36 FREQ input Switching-frequency select: low = 500kHz, high = 1MHz.
37 ITEC output TEC current monitor output; VITEC = 1.50V + (VOS1 - VCS) × 8.
38 COMP passive Current-control loop compensation; for most designs connect a 10nF capacitor from COMP to GND.
39 MAXIP input Maximum positive TEC current; connect to REF to set the default positive current limit of +150mV/RSENSE.
40 MAXIN input Maximum negative TEC current; connect to REF to set the default negative current limit of -150mV/RSENSE, and connect to MAXIP when using the MAX1979.
41 MAXV input Maximum bipolar TEC voltage; connect an external resistive divider from REF to GND to set it, with maximum TEC voltage equal to 4 × VMAXV.
42 GND power_in Analog ground; connect all GND pins to the analog ground plane.
43 GND power_in Analog ground; connect all GND pins to the analog ground plane.
44 VDD power_in Analog supply voltage input (3.0V to 5.5V); bypass to GND with a 10µF ceramic capacitor.
45 CTLI input TEC current-control input that sets differential current into the TEC, with center point at 1.50V (no TEC current); connect to INTOUT when using the thermal control loop.
46 REF power_out 1.5V reference voltage output; bypass REF to GND with a 1µF ceramic capacitor.
47 CS input Current-sense input; TEC current is monitored between CS and OS1, with maximum TEC current given by 150mV/RSENSE and bipolar for the MAX1978.
48 OS1 input Output Sense 1 senses one side of the differential TEC voltage and is a sense point, not a power output.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TQFN-48-EP(7x7)
Category Power Management (PMIC)
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Range VDD 3 5.5 V TA = -40°C to +85°C 5
Output Voltage Range (MAX1978) VOUT -4.3 4.3 V VDD=5V, ITEC=0 to ±3A, VOUT=VOS1-VOS2 5
Output Voltage Range (MAX1978) VOUT -2.3 2.3 V VDD=3V, ITEC=0 to ±3A, VOUT=VOS1-VOS2 5
Output Voltage Range (MAX1979) VOUT 4.3 V VDD=5V, ITEC=0 to 6A, VOUT=VOS1 5
Maximum TEC Current (MAX1978) ITEC(MAX) -3 3 A Printed as ±3 5
Maximum TEC Current (MAX1979) ITEC(MAX) 6 A Unipolar 5
Reference Voltage VREF 1.475 1.515 V VDD=3V to 5.5V, IREF=150µA 5
Reference Load Regulation ΔVREF 5 mV VDD=3V to 5.5V, IREF=10µA to -1mA 5
Current-Sense Threshold 135 160 mV VOS1 < VCS, VMAXI_ = VREF 5
Current-Sense Threshold 40 60 mV VOS1 < VCS, VMAXI_ = VREF/3 5
Current-Sense Threshold 135 160 mV VOS1 > VCS, VMAXI_ = VREF 5
Current-Sense Threshold 40 60 mV VOS1 > VCS, VMAXI_ = VREF/3 5
No-Load Supply Current IDD(NOLOAD) 50 mA VDD=5V 5
No-Load Supply Current IDD(NOLOAD) 30 mA VDD=3.3V 5
Shutdown Supply Current IDD-SD 3 mA SHDN=GND, VDD=5V (Note 3) 5
UVLO Threshold (rising) VUVLO 2.4 2.8 V VDD rising 5
UVLO Threshold (falling) VUVLO 2.25 2.75 V VDD falling 5
Switching Frequency Internal fSW-INT 450 650 kHz FREQ = GND 5
Switching Frequency Internal fSW-INT 800 1200 kHz FREQ = VDD 5
OS1, OS2, CS Input Current IOS1, IOS2, ICS -100 100 µA 0 or VDD 5
SHDN, FREQ Input Current ISHDN, IFREQ -5 5 µA 0 or VDD 5
SHDN, FREQ Input Low Voltage VIL 0.25 × VDD VDD = 3V to 5.5V; printed as 0.25 × VDD 5
SHDN, FREQ Input High Voltage VIH 0.75 × VDD VDD = 3V to 5.5V; printed as 0.75 × VDD 5
MAXV Threshold Accuracy -1 1 % VMAXV = VREF × 0.67, VOS1 to VOS2 = ±4V, VDD = 5V 6
MAXV Threshold Accuracy -2 2 % VMAXV = VREF × 0.33, VOS1 to VOS2 = ±2V, VDD = 3V 6
MAXV, MAXIP, MAXIN Input Bias Current IMAXV-BIAS, IMAXI_-BIAS -0.1 0.1 µA VMAXV = VMAXI_ = 0.1V or 1.5V 6
CTLI Gain ACTLI 9.5 10.5 V/V VCTLI = 0.5V to 2.5V (Note 4) 6
CTLI Input Resistance RCTLI 0.5 2 MΩ 1MΩ terminated at REF 6
Error Amp Transconductance gm 50 175 µS 6
ITEC Accuracy -10 10 % VOS1 to VCS = +100mV or -100mV 6
ITEC Load Regulation ΔVITEC -0.125 0.125 % VOS1 to VCS = ±100mV, IITEC = ±10µA 6
Instrumentation Amp Input Bias Current IDIF-BIAS -10 10 nA 6
Instrumentation Amp Offset Voltage VDIF-OS -200 200 µV VDD = 3V to 5.5V 6
Instrumentation Amp Preset Gain ADIF 45 55 V/V RLOAD = 10kΩ to REF 6
Integrator Amp Input Bias Current IINT-BIAS 1 nA VDD = 3V to 5.5V 6
Integrator Amp Voltage Offset VINT-OS -3 3 mV VDD = 3V to 5.5V 6
Undedicated Chopper Amp Input Bias Current IAIN-BIAS -10 10 nA VDD = 3V to 5.5V 6
Undedicated Chopper Amp Offset Voltage VAIN-OS -200 200 µV VDD = 3V to 5.5V 6
BFB_ Buffer Error -200 200 µV CLOAD < 100pF 6
UT and OT Leakage Current ILEAK 1 µA VUT = VOT = 5.5V 6
UT and OT Output Low Voltage VOL 150 mV Sinking 4mA 6
NFET On-Resistance RDS(ON-N) 0.04 0.07 Ω VDD = 5V, I = 0.5A (25°C typ table) 2
NFET On-Resistance RDS(ON-N) 0.06 0.08 Ω VDD = 3V, I = 0.5A (25°C typ table) 2
PFET On-Resistance RDS(ON-P) 0.06 0.1 Ω VDD = 5V, I = 0.5A (25°C typ table) 2
PFET On-Resistance RDS(ON-P) 0.09 0.12 Ω VDD = 3V, I = 0.5A (25°C typ table) 2
NFET Leakage ILEAK(N) 0.02 10 µA VLX = VDD = 5V, TA = +25°C 2
PFET Leakage ILEAK(P) 0.02 10 µA VLX = 0, TA = +25°C 3
Absolute maximum: VDD to GND VDD -0.3 6 V 2
Absolute maximum: SHDN, MAXV, MAXIP, MAXIN, CTLI, OT, UT to GND -0.3 6 V 2
Absolute maximum: FREQ, COMP, OS1, OS2, CS, REF, ITEC, AIN+, AIN-, AOUT, INT-, INTOUT, BFB+, BFB-, FB+, FB-, DIFOUT to GND -0.3 V Upper limit printed as VDD + 0.3V 2
Absolute maximum: PVDD1, PVDD2 to VDD -0.3 0.3 V 2
Absolute maximum: PVDD1, PVDD2 to GND -0.3 V Upper limit printed as VDD + 0.3V 2
Absolute maximum: PGND1, PGND2 to GND -0.3 0.3 V 2
Peak LX Current (MAX1978) -4.5 4.5 A Printed as ±4.5A (Note 1) 2
Peak LX Current (MAX1979) 9 A Printed as +9A (Note 1) 2
Storage Temperature Range -65 150 °C 2
Operating Temperature Range (MAX1978ETM) -40 85 °C 2
Maximum Junction Temperature TJ 150 °C 2
Thermal Shutdown TSHUTDOWN 165 °C Hysteresis = 15°C 3

CAD (KiCad official)

  • Symbol: MAX1978ETM+T
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: TQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: max1978etm-t-etched.step / max1978etm-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max1978etm-t.step / max1978etm-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (20 pp, sha256 5d018f9866db0f80, retrieved 2026-10-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF