MAX17614ATP+ from ANALOG DEVICES, in a TQFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN	power_in	Input pin; connect a low-ESR ceramic capacitor to enhance ESD protection, and see the Applications Information section for hot plug-in applications.
2	IN	power_in	Input pin; connect a low-ESR ceramic capacitor to enhance ESD protection, and see the Applications Information section for hot plug-in applications.
3	IN	power_in	Input pin; connect a low-ESR ceramic capacitor to enhance ESD protection, and see the Applications Information section for hot plug-in applications.
4	UVLO	input	Input undervoltage lockout adjustment; connect to the mid-point of a resistive divider from IN to GND to set the input UVLO threshold (UVLO threshold rising 1.50V typ, falling 1.45V typ).
5	OVLO	input	Input overvoltage lockout adjustment; connect to the mid-point of a resistor divider from IN to GND to set the input OVLO threshold.
6	CLMODE	input	Current-limit mode selector: connect to GND for Continuous mode, a 150kΩ resistor to GND for Latch-off mode, or leave unconnected for Autoretry mode.
7	SETI	bidirectional	Overcurrent limit adjustment pin and current monitoring output; connect a resistor from SETI to GND to set the overcurrent limit, and do not connect more than 10pF to SETI.
8	GND	power_in	Ground reference for the device.
9	EN	input	Active-high enable input, internally pulled up to 1.4V; leave unconnected for always-ON operation.
10	UVOV	output	Open-drain fault indicator output that goes high when the input falls below the UVLO falling threshold or rises above the OVLO rising threshold.
11	FLAG	output	Open-drain fault indicator output that goes low on overcurrent blanking-time expiry, failed startup output rise, reverse current detection, thermal shutdown, or RSETI below 1.5kΩ (max).
12	TSTART	passive	Startup blanking time programming input; connect a capacitor to GND to set the blanking time, or leave unconnected for a default startup blanking time of 100ms.
13	OUT	power_out	Output pin; see the Applications Information section for long output cables or inductive loads.
14	OUT	power_out	Output pin; see the Applications Information section for long output cables or inductive loads.
15	OUT	power_out	Output pin; see the Applications Information section for long output cables or inductive loads.
16	NC	unconnected	Not connected.
17	NC	unconnected	Not connected.
18	NC	unconnected	Not connected.
19	NC	unconnected	Not connected.
20	NC	unconnected	Not connected.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	ANALOG DEVICES
Package	TQFN-20-EP(4x4)
Category	Global Sourcing Parts
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
IN Voltage Range	VIN	4.5		60	V		2
Shutdown Input Current	ISHDN	33		75	μA	VEN = 0V	2
Reverse Input Current	IIN_RVS	-100		-58	μA	VIN = -60V, VOUT = 0V	2
Supply Current	IIN	1.02		1.35	mA	VIN = 24V	2
Internal Undervoltage Trip Level (rising)	VINT_UVR	3.46	4.2	4.5	V	VIN rising	2
Internal Undervoltage Trip Level (falling)	VINT_UVF	3.2	3.46	4	V	VIN falling	2
UVLO Threshold (rising)	VUVR	1.47	1.5	1.53	V	VUVLO rising	2
UVLO Threshold (falling)	VUVF	1.42	1.45	1.48	V	VUVLO falling	2
OVLO Threshold (rising)	VOVR	1.47	1.5	1.53	V	VOVLO rising	3
OVLO Threshold (falling)	VOVF	1.42	1.45	1.48	V	VOVLO falling	3
UVLO, OVLO Leakage Current	ILEAK	-100		100	nA	VUVLO = VOVLO = 0 to 2V	3
OVLO Adjustment Range		5.5		60	V		3
UVLO Adjustment Range		4.5		59	V		3
Internal FETs On-Resistance	RON		130	155	mΩ	ILOAD = 100mA, VIN > 8V, TJ = +25°C	3
Internal FETs On-Resistance	RON			200	mΩ	ILOAD = 100mA, VIN > 8V, TJ = +85°C	3
Internal FETs On-Resistance	RON			230	mΩ	ILOAD = 100mA, VIN > 8V, -40°C ≤ TJ ≤ +125°C	3
Current Limit Adjustment Range	ILIM	0.15		3	A		3
Current Limit Accuracy		-3.3		3.6	%	0.15A ≤ ILIM ≤ 0.3A	3
Current Limit Accuracy		-3.3		3.3	%	0.3A ≤ ILIM ≤ 3A	3
Overcurrent Protection Threshold	IOCP	4	8.5	15	A		3
FLAG Assertion Drop Voltage Threshold	VFA	410	470	550	mV	Increase (VIN - VOUT) drop until FLAG asserts, VIN = 24V	3
Slow Reverse Current Blocking Threshold	VRIBS	-8.6	-4.5	-0.3	mV	(VIN - VOUT)	3
Slow Reverse Current Blocking Debounce Blanking Time	tDEBRIB	10	17	35	μs		3
Fast Reverse Current Blocking Threshold	VRIBF	-130	-102	-68	mV	(VIN - VOUT)	3
Fast Reverse Current Blocking Response Time	tRIB	90	140	220	ns		3
Reverse Blocking Exit Threshold	VRIB_RISING	67	100	123	mV	(VIN - VOUT)	3
Reverse Blocking Supply Current	IRBL	1.06		1.4	mA	Current into OUT when (VOUT - VIN) > 130mV	3
Current Mirror Output Ratio	CIRATIO	2952	3032	3117	A/A	0.15A ≤ IIN ≤ 0.3A	3
Current Mirror Output Ratio	CIRATIO	2964	3032	3128	A/A	0.3A ≤ IIN ≤ 3A	3
Internal SETI Clamp	VSETI_MAX	1.6		2.2	V	5mA into SETI	3
SETI Leakage Current		-0.1		0.1	μA	VSETI = 1.6V	3
EN Pull-Up Voltage		1.4		2	V	EN pin unconnected. VIN = 60V	4
EN Input Current		13		40	μA	VEN = 5.5V	4
EN Pull-Up Current		1	6.2	15	μA	VEN = 0.4V	4
CLMODE Input Logic High		2	4.2	4.9	V		4
CLMODE Input Logic Low		0.25	0.6	0.95	V		4
TSTART Reference Voltage	VTSTART-REF	1.43	1.5	1.57	V		4
TSTART Output Current	ISTART	4.5	5	5.5	µA		4
TSTART Default Interval	tSTART-DEFAULT	90	100	110	ms		4
Q2 Turn-On Delay (OVLO)	tQ2_ON_OVLO	18		26	μs	ILOAD = 3A, From VOVLO < VOVF to IOUT = 95%	4
Q2 Turn-On Delay (UVLO)	tQ2_ON_UVLO	1.15		1.8	ms	ILOAD = 3A, From VUVLO > VUVR to IOUT = 95%	4
OVLO Rising Edge Delay	tOVR_DLY	0.86		1.5	µs	From VOVLO > VOVR to VOUT = 90%; RLOAD = 1kΩ, CLOAD = 0pF	4
IN Debounce Time	tDEB	0.75	1.25	2	ms	From (VIN_UVR < VIN < VIN_OVR) and (EN = High) to VOUT = 10% of VIN; elapses only at power-up; VIN = 24V	4
Current Limit Blanking Time	tBLANK	18	20	22	ms		4
Current Limit Autoretry Time	tRETRY	900	1000	1100	ms	After blanking time from IOUT > ILIM to FLAG deasserted	4
IN to GND		-70		65	V		2
IN to OUT		-65		65	V		2
OUT to GND		-0.3		65	V		2
UVLO, OVLO to GND		-0.3			V	Max printed as (max(VIN, VOUT)+0.3)V	2
EN, CLMODE, TSTART to GND		-0.3		6	V		2
UVOV, FLAG to GND		-0.3		6	V		2
IN Current (DC)				3.3	A		2
SETI to GND		-0.3		1.6	V	Note 1: pin internally clamped; forcing >5mA can damage device	2
Continuous Power Dissipation				2424.2	mW	TA = +70°C, derate 30.3mW/°C above +70°C	2
Operating Temperature Range		-40		125	°C	Note 2: junction temp above +125°C degrades operating life	2
Junction Temperature Range	TJ	-40		150	°C		2
Storage Temperature Range		-65		150	°C		2
Maximum Slew Rate at IN Pins				100	V/µs	IN pins; same 100V/µs limit stated for OUT pins	33
Junction-to-Ambient Thermal Resistance	θJA		33		°C/W	Four-layer board, JESD51-7	2

CAD (KiCad official)

Symbol: MAX17614ATP+
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: TQFN-20-EP(4x4) (KiCad packages3D, STEP)
3D model files: max17614atp-etched.step / max17614atp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max17614atp.step / max17614atp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ANALOG DEVICES datasheet (38 pp, sha256 9a929c84226d612e, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MAX17614ATP+

Verified MAX17614ATP+

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README