component

MAX17544ATP+

Public Made by Adom

by adom

Maxim Integrated DC-DC Converters, TQFN-20(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsmax17544atp+factory-2.0.0extractor-text

Verified MAX17544ATP+

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 21 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MAX17544ATP+ · TQFN-20(5x5) · 21 pins
  • ✓copper: 21 copper pads, none touching another net
  • ✓datasheet: all 21 pin names found in the 21-page datasheet
  • ✓distributor: lcsc C1355290, digikey MAX17544ATP+-ND, mouser 700-MAX17544ATP+
  • ✓family: QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-aggph0jb/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 21 pins = 21 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 21 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ max17544atp.kicad_sym✓ max17544atp.kicad_mod✓ max17544atp.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
max17544atp / README.md
History Download
Ray Publish 0.1.0 ddda7d0 6d ago

MAX17544ATP+

Maxim Integrated · DC-DC Converters · TQFN-20(5x5)

MAX17544ATP+ from Maxim Integrated, in a TQFN-20(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Power supply input with a 4.5V to 42V input supply range; connect the VIN pins together.
2 VIN power_in Power supply input with a 4.5V to 42V input supply range; connect the VIN pins together.
3 VIN power_in Power supply input with a 4.5V to 42V input supply range; connect the VIN pins together.
4 EN/UVLO input Enable/undervoltage lockout input that must be driven high to enable the output, with an external resistor divider from VIN to SGND setting the turn-on input voltage.
5 RESET output Open-drain RESET output that is driven low if FB drops below 92% of its set value and goes high 1024 clock cycles after FB rises above 95% of its set value.
6 SYNC input Clock input used to synchronize the device to an external clock.
7 SS passive Soft-start input; a capacitor connected from SS to SGND sets the soft-start time.
8 CF passive At switching frequencies below 500kHz a capacitor is connected from CF to FB, and CF is left open at 500kHz or above.
9 FB input Feedback input connected to the center tap of an external resistor divider from the output to GND to set the output voltage.
10 RT passive A resistor from RT to SGND sets the switching frequency from 100kHz to 2.2MHz, and leaving RT open selects the default 500kHz.
11 MODE input Mode select pin: left unconnected for PFM, connected to SGND for constant-frequency PWM, and connected to VCC for DCM operation, latched at power-up.
12 VCC power_out 5V LDO output that must be bypassed with 2.2µF ceramic capacitance to SGND.
13 SGND power_in Analog ground.
14 PGND power_in Power ground that connects externally to the power ground plane and to SGND at the VCC bypass capacitor return path.
15 PGND power_in Power ground that connects externally to the power ground plane and to SGND at the VCC bypass capacitor return path.
16 PGND power_in Power ground that connects externally to the power ground plane and to SGND at the VCC bypass capacitor return path.
17 LX output Switching node connected to the switching side of the inductor.
18 LX output Switching node connected to the switching side of the inductor.
19 LX output Switching node connected to the switching side of the inductor.
20 BST passive Boost flying capacitor connection; a 0.1µF ceramic capacitor is connected between BST and LX.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package TQFN-20(5x5)
Category Power Management ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN to PGND VIN -0.3 48 V VIN to PGND 2
EN/UVLO to SGND VEN/UVLO -0.3 48 V EN/UVLO to SGND 2
BST to PGND VBST -0.3 53 V BST to PGND 2
BST to LX VBST-LX -0.3 6.5 V BST to LX 2
BST to VCC VBST-VCC -0.3 48 V BST to VCC 2
CF, RESET, SS, MODE, SYNC, RT to SGND -0.3 6.5 V CF, RESET, SS, MODE, SYNC, RT to SGND 2
FB to SGND VFB -0.3 1.5 V FB to SGND 2
VCC to SGND VCC -0.3 6.5 V VCC to SGND 2
SGND to PGND -0.3 0.3 V SGND to PGND 2
LX Total RMS Current ILX -5.6 5.6 A LX total RMS current 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range TSTG -65 160 °C 2
Lead Temperature 300 °C soldering, 10s 2
Soldering Temperature (reflow) 260 °C reflow 2
Input Voltage Range VIN 4.5 42 V 2
Input Shutdown Current IIN-SH 2.8 4.5 µA VEN/UVLO = 0V (shutdown mode) 2
Input Quiescent Current DCM IQ-DCM 1.16 1.8 mA DCM mode, VLX = 0.1V 2
EN/UVLO Threshold rising VENR 1.19 1.215 1.26 V VEN/UVLO rising 2
EN/UVLO Threshold falling VENF 1.068 1.09 1.131 V VEN/UVLO falling 2
EN/UVLO Input Leakage Current IEN -50 0 50 nA VEN/UVLO = 0V, TA = +25°C 2
VCC Output Voltage Range VCC 4.75 5 5.25 V 6V < VIN < 42V, IVCC = 1mA 2
VCC Output Voltage Range (load) VCC 4.75 5 5.25 V 1mA ≤ IVCC ≤ 25mA 2
VCC Current Limit IVCC-MAX 26.5 54 100 mA VCC = 4.3V, VIN = 6V 2
VCC UVLO rising VCC_UVR 4.05 4.2 4.3 V VCC rising 2
VCC UVLO falling VCC_UVF 3.65 3.8 3.9 V VCC falling 2
High-Side nMOS On-Resistance RDS-ONH 165 325 mΩ ILX = 0.3A 3
Low-Side nMOS On-Resistance RDS-ONL 80 150 mΩ ILX = 0.3A 3
LX Leakage Current ILX_LKG -2 2 µA VLX = VIN - 1V, VLX = VPGND + 1V, TA = +25°C 3
Soft-Start Charging Current ISS 4.7 5 5.3 µA VSS = 0.5V 3
FB Regulation Voltage (MODE = SGND or VCC) VFB_REG 0.89 0.9 0.91 V MODE = SGND or MODE = VCC 3
FB Regulation Voltage (MODE open) VFB_REG 0.89 0.915 0.936 V MODE = OPEN 3
FB Input Bias Current IFB -50 50 nA 0 < VFB < 1V, TA = +25°C 3
Peak Current-Limit Threshold IPEAK-LIMIT 4.4 5.1 5.85 A 3
Runaway Current-Limit Threshold IRUNAWAY-LIMIT 4.9 5.7 6.7 A 3
Valley Current-Limit Threshold ISINK-LIMIT -0.16 0 0.16 A MODE = open/VCC 3
PFM Current-Limit Threshold IPFM 0.6 0.75 0.9 A MODE = open 3
Switching Frequency fSW 90 100 110 kHz RRT = 210kΩ 3
Switching Frequency fSW 180 200 220 kHz RRT = 102kΩ 3
Switching Frequency fSW 475 500 525 kHz RRT = 40.2kΩ 3
Switching Frequency fSW 1950 2200 2450 kHz RRT = 8.06kΩ 3
Switching Frequency fSW 460 500 540 kHz RRT = open 3
FB Undervoltage Trip Level to Cause Hiccup VFB-HICF 0.56 0.58 0.65 V 3
FB Threshold for RESET Assertion VFB-OKF 90.5 92 94.6 %VFB-REG VFB falling 4
FB Threshold for RESET Deassertion VFB-OKR 93.8 95 97.8 %VFB-REG VFB rising 4
RESET Output Leakage Current -0.1 0.1 µA TA = TJ = +25°C, VRESET = 5.5V 4
Input Quiescent Current PFM (VFB=1V, MODE=RT=open) IQ_PFM 118 µA VFB = 1V, MODE = RT = open 2
Input Quiescent Current PFM (VFB=1V, MODE=open) IQ_PFM 162 µA VFB = 1V, MODE = open 2
Junction-to-Ambient Thermal Resistance θJA 30 °C/W 2
Junction-to-Case Thermal Resistance θJC 2 °C/W 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper Exposed Pad. Connect to the SGND pin. Connect to a large copper plane below the IC to improve heat 11

CAD (KiCad official)

  • Symbol: MAX17544ATP+
  • Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
  • 3D model: TQFN-20(5x5) (KiCad packages3D, STEP)
  • 3D model files: max17544atp-etched.step / max17544atp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max17544atp.step / max17544atp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (21 pp, sha256 ce246f2733327f1f, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF