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MAX17525ATP+T
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Analog Devices Inc Maxim Integrated Power Management - Specialized, TQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MAX17525ATP+T
Analog Devices Inc Maxim Integrated · Power Management - Specialized · TQFN-20-EP(5x5)
MAX17525ATP+T from Analog Devices Inc Maxim Integrated, in a TQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Switch input; bypass IN to ground with a 1µF ceramic capacitor (10nF to 100nF at IN when an external pFET is used, with 4.7µF at the pFET drain), and the maximum slew rate allowed at IN is 30V/µs. |
| 2 | IN | power_in | Switch input; bypass IN to ground with a 1µF ceramic capacitor (10nF to 100nF at IN when an external pFET is used, with 4.7µF at the pFET drain), and the maximum slew rate allowed at IN is 30V/µs. |
| 3 | IN | power_in | Switch input; bypass IN to ground with a 1µF ceramic capacitor (10nF to 100nF at IN when an external pFET is used, with 4.7µF at the pFET drain), and the maximum slew rate allowed at IN is 30V/µs. |
| 4 | IN | power_in | Switch input; bypass IN to ground with a 1µF ceramic capacitor (10nF to 100nF at IN when an external pFET is used, with 4.7µF at the pFET drain), and the maximum slew rate allowed at IN is 30V/µs. |
| 5 | IN | power_in | Switch input; bypass IN to ground with a 1µF ceramic capacitor (10nF to 100nF at IN when an external pFET is used, with 4.7µF at the pFET drain), and the maximum slew rate allowed at IN is 30V/µs. |
| 6 | GP | output | Gate driver output for the external pFET. |
| 7 | SETI | input | Overload current-limit adjust; a resistor from SETI to GND programs the overcurrent limit, SETI must be connected to a resistor (the switch does not turn on if SETI is tied to GND during startup), and no more than 30pF may be connected to SETI. |
| 8 | FLAG | output | Open-drain fault indicator that asserts low when VIN - VOUT exceeds VFA, reverse current is detected, thermal shutdown is active, the OVLO or UVLO threshold is reached, or SETI is connected to GND. |
| 9 | OVLO | input | Externally programmable overvoltage-lockout threshold; connect to GND for the internal default threshold or to an external resistor divider to override it. |
| 10 | UVLO | input | Externally programmable undervoltage-lockout threshold; connect to GND for the internal default threshold or to an external resistor divider to override it. |
| 11 | OUT | power_out | Switch output; bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to the device. |
| 12 | OUT | power_out | Switch output; bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to the device. |
| 13 | OUT | power_out | Switch output; bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to the device. |
| 14 | OUT | power_out | Switch output; bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to the device. |
| 15 | OUT | power_out | Switch output; bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to the device. |
| 16 | RIPEN | input | Reverse-current protection enable; connect to GND through a 10kΩ pulldown to disable reverse-current flow protection, and leave open or tie to logic-high to activate it. |
| 17 | HVEN | input | 60V-capable active-low enable input; see Table 1 in the datasheet for its operation. |
| 18 | CLTS2 | input | Current-limit type select 2; see Table 2 in the datasheet for its operation. |
| 19 | CLTS1 | input | Current-limit type select 1; see Table 2 in the datasheet for its operation. |
| 20 | EN | input | Active-high enable input; see Table 1 in the datasheet for its operation. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | TQFN-20-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN Voltage Range | VIN | 5.5 | 60 | V | 3 | ||
| Shutdown IN Current | ISHDN | 4 | 15 | µA | VEN = 0V, VHVEN = 5V, VIN < 40V | 3 | |
| Shutdown IN Current | ISHDN | 4 | 150 | µA | VEN = 0V, VHVEN = 5V | 3 | |
| Supply Current | IIN | 1.4 | 2.16 | mA | VIN = VOUT = 24V, VHVEN = 0V | 3 | |
| Shutdown OUT Current | IOFF | 50 | 100 | µA | VEN = 0V, VHVEN = 5V | 3 | |
| Internal UVLO Trip Level (VIN falling) | VUVLO | 11.5 | 12 | 12.5 | V | VIN falling, UVLO trip point | 3 |
| Internal UVLO Trip Level (VIN rising) | VUVLO | 11.9 | 12.4 | 13.1 | V | VIN rising | 3 |
| Internal OVLO Trip Level (VIN falling) | VOVLO | 32.2 | 34.1 | 35.8 | V | VIN falling | 3 |
| Internal OVLO Trip Level (VIN rising) | VOVLO | 34.7 | 36.2 | 37.6 | V | VIN rising, OVLO trip point | 3 |
| External UVLO Adjustment Range | 5.5 | 24 | V | Note 4 (not production-tested, user-adjustable) | 3 | ||
| External OVLO Adjustment Range | 6 | 40 | V | Note 4 (not production-tested, user-adjustable) | 3 | ||
| External UVLO Select Voltage | VUVLO_SEL | 0.15 | 0.38 | 0.5 | V | 3 | |
| External OVLO Select Voltage | VOVLO_SEL | 0.15 | 0.38 | 0.5 | V | 3 | |
| External UVLO Leakage Current | IUVLO_LEAK | -250 | 250 | nA | 3 | ||
| External OVLO Leakage Current | IOVLO_LEAK | -250 | 250 | nA | 3 | ||
| External UVLO/OVLO Set Voltage | VSET | 1.18 | 1.22 | 1.27 | V | 3 | |
| Undervoltage Trip Level on OUT (VOUT falling) | VUVLO_OUT | 11.5 | 12 | 12.5 | V | VOUT falling, UVLO trip point | 3 |
| Undervoltage Trip Level on OUT (VOUT rising) | VUVLO_OUT | 11.9 | 12.4 | 13 | V | VOUT rising | 3 |
| GP Gate Clamp Voltage | VGP | 10 | 16.1 | 20 | V | 3 | |
| Gate Active Pullup | 11 | 22 | Ω | 3 | |||
| Gate Active Pulldown | 47 | 110 | µA | VEN = 5V | 3 | ||
| Internal FET On-Resistance | RON | 31 | 44 | mΩ | ILOAD = 100mA, VIN ≥ 10V, TA = +25ºC | 3 | |
| Current Limit Adjustment Range | ILIM | 0.6 | 6 | A | 3 | ||
| Current Limit Accuracy | ILIM_ACC | -10 | 10 | % | 1A ≤ ILIM ≤ 6A (TA = +25°C) | 3 | |
| Current Limit Accuracy | ILIM_ACC | -15 | 15 | % | 0.6A ≤ ILIM ≤ 6A | 3 | |
| Slow Reverse Current-Blocking Threshold | VRIB_SLOW | -0.5 | -5.4 | -10.5 | mV | VIN - VOUT | 4 |
| Slow Reverse Current-Blocking Response Time | tRIB_SLOW | 17 | 30 | µs | See the Slow Reverse-Current Fault Timing Diagram | 4 | |
| Fast Reverse Current-Blocking Threshold | VRIB_FAST | -85 | -100 | -115 | mV | VIN - VOUT | 4 |
| Fast Reverse Current-Blocking Response Time | tRIB_FAST | 0.7 | 1 | µs | (VIN - VOUT) changes from 0.2V to -0.3V in 100nsec, CIN-GP = 5nF | 4 | |
| Reverse-Blocking Supply Current | IRBS | 3280 | 5110 | µA | VOUT = 24V | 4 | |
| HVEN Threshold Voltage | VHVEN_TH | 1 | 2 | 3.1 | V | 4 | |
| HVEN Input Leakage Current | IHVEN_LEAK | 51 | 72 | µA | VHVEN = 60V | 4 | |
| EN, RIPEN, CLTS1, CLTS2 Input Logic-High | VIH | 1.4 | V | 4 | |||
| EN, RIPEN, CLTS1, CLTS2 Input Logic-Low | VIL | 0.4 | V | 4 | |||
| EN Input Leakage Current | IEN_LEAK | -1 | 1 | µA | VEN = 0V, 5V | 4 | |
| FLAG Logic-Low Voltage | 0.4 | V | ISINK = 1mA | 4 | |||
| Fault Recovery nFET Turn-On Time | tON_NFET | 200 | 500 | µs | Turn-on delay after fault timers expired | 5 | |
| Fault Recovery pFET Turn-On Time | tON_PFET | 1.08 | 1.2 | 1.32 | ms | VOUT > VUVLO_OUT, turn-on delay of pFET after fault timers expired | 5 |
| Reverse-Current Fault Recovery Time | tREV_REC | 0.4 | 0.45 | 0.5 | ms | 5 | |
| Startup Timeout | tSTO | 1090 | 1200 | 1320 | ms | Initial start current-limit foldback timeout (Figure 1) | 5 |
| Startup Initial Time | tSTI | 21.8 | 24 | 26.4 | ms | Current is continuously limited to 1x in this interval (Figure 1) | 5 |
| IN Debounce Time | tDEB | 1.09 | 1.2 | 1.32 | ms | Additional turn-on delay if VOUT < VUVLO_OUT, see the Timing Diagrams | 5 |
| Blanking Time | tBLANK | 21.8 | 24 | 26.4 | ms | Figures 3 and 4 | 5 |
| Autoretry Time | tRETRY | 554 | 720 | 792 | ms | Figure 3, Note 6 | 5 |
| IN Pin Absolute Maximum Voltage | VIN | -0.3 | 62 | V | All voltages referenced to GND; Note 1 | 2 | |
| OUT Pin Absolute Voltage | VOUT | -0.3 | V | Upper limit VIN + 0.3V | 2 | ||
| HVEN Pin Absolute Voltage | VHVEN | -0.3 | V | Upper limit VIN + 0.3V; Note 1 | 2 | ||
| UVLO, OVLO Pin Absolute Voltage | -0.3 | 20 | V | Upper limit min(VIN + 0.3V, 20V) | 2 | ||
| FLAG, EN, RIPEN, CLTS1, CLTS2 Absolute Voltage | -0.3 | 6 | V | 2 | |||
| SETI Pin Absolute Voltage | -0.3 | 6 | V | Upper limit min(VIN + 0.3V, 6V) | 2 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | 2 | ||
| Junction Temperature | TJ | 150 | °C | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature (soldering) | 300 | °C | Soldering, 10s | 2 | |||
| Junction to Ambient Thermal Resistance | θJA | 29 | °C/W | Four-layer board, JESD51-7 | 2 | ||
| Junction to Case Thermal Resistance | θJC | 2 | °C/W | Four-layer board, JESD51-7 | 2 | ||
| Thermal Foldback | TJ_FB | 150 | °C | 5 | |||
| Thermal Shutdown | TJ_MAX | 170 | °C | 5 | |||
| Fast Flag Assertion Drop Voltage Threshold | VFA | 490 | mV | Increase in (VIN - VOUT) drop until FLAG asserts, VIN = 24V | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | five OUT pins and needs to be dissipated on this same copper area. | 19 |
CAD (KiCad official)
- Symbol:
MAX17525ATP+T - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: TQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
max17525atp-t-etched.step/max17525atp-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max17525atp-t.step/max17525atp-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (21 pp, sha256
a1b13272a965e9c8, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).