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MAX17503ATP+T
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Analog Devices Inc Maxim Integrated DC-DC Converters, TQFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMAX17503ATP+T
Analog Devices Inc Maxim Integrated · DC-DC Converters · TQFN-20-EP(4x4)
MAX17503ATP+T from Analog Devices Inc Maxim Integrated, in a TQFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power-supply input with a 4.5V to 60V input supply range; connect the VIN pins together and decouple to PGND with a 2.2µF capacitor placed close to the VIN and PGND pins. |
| 2 | VIN | power_in | Power-supply input with a 4.5V to 60V input supply range; connect together with the other VIN pins and decouple to PGND with a 2.2µF capacitor placed close to the VIN and PGND pins. |
| 3 | VIN | power_in | Power-supply input with a 4.5V to 60V input supply range; connect together with the other VIN pins and decouple to PGND with a 2.2µF capacitor placed close to the VIN and PGND pins. |
| 4 | EN/UVLO | input | Enable/undervoltage lockout: drive high to enable the output, connect to the center of a VIN-to-SGND resistor divider to set the turn-on input voltage, or pull up to VIN for always-on operation. |
| 5 | RESET | output | Open-drain RESET output that is driven low if FB drops below 92% of its set value and goes high 1024 clock cycles after FB rises above 95% of its set value. |
| 6 | SYNC | input | External clock synchronization input that synchronizes the device switching frequency to an external clock, as described in the External Frequency Synchronization (SYNC) section. |
| 7 | SS | input | Soft-start input; connect a capacitor from SS to SGND to set the soft-start time. |
| 8 | CF | passive | Connect a capacitor from CF to FB at switching frequencies below 500kHz, and leave CF open for switching frequencies of 500kHz or higher. |
| 9 | FB | input | Feedback input; connect to the center tap of an external resistor divider from the output to GND to set the output voltage. |
| 10 | RT | passive | Connect a resistor from RT to SGND to set the switching frequency; leave RT open for the default 500kHz frequency. |
| 11 | MODE | input | Mode select latched at power-up: leave open for PFM, connect to SGND for constant-frequency PWM at all loads, or connect to VCC for constant-frequency DCM at light loads. |
| 12 | VCC | power_out | 5V LDO output that must be bypassed to SGND with 2.2µF ceramic capacitance. |
| 13 | SGND | power_in | Analog ground; the SGND and PGND pins are connected together at the ground return path of the VCC bypass capacitor. |
| 14 | PGND | power_in | Power ground; connect externally to the power ground plane and tie to SGND at the return path of the VCC bypass capacitor. |
| 15 | PGND | power_in | Power ground; connect externally to the power ground plane and tie to SGND at the return path of the VCC bypass capacitor. |
| 16 | PGND | power_in | Power ground; connect externally to the power ground plane and tie to SGND at the return path of the VCC bypass capacitor. |
| 17 | LX | output | Switching node connected to the switching side of the inductor; the datasheet specifies LX total RMS current of ±4A absolute maximum. |
| 18 | LX | output | Switching node connected to the switching side of the inductor; connect all LX pins to the inductor switching side. |
| 19 | LX | output | Switching node connected to the switching side of the inductor; connect all LX pins to the inductor switching side. |
| 20 | BST | passive | Boost flying capacitor pin; connect a 0.1µF ceramic capacitor between BST and LX. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | TQFN-20-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to PGND | -0.3 | 65 | V | 2 | |||
| EN/UVLO to SGND | -0.3 | 65 | V | 2 | |||
| LX to PGND (max printed as VIN + 0.3V) | -0.3 | V | 2 | ||||
| BST to PGND | -0.3 | 70 | V | 2 | |||
| BST to LX | -0.3 | 6.5 | V | 2 | |||
| BST to VCC | -0.3 | 65 | V | 2 | |||
| CF, RESET, SS, MODE, SYNC, RT to SGND | -0.3 | 6.5 | V | 2 | |||
| FB to SGND | -0.3 | 1.5 | V | 2 | |||
| VCC to SGND | -0.3 | 6.5 | V | 2 | |||
| SGND to PGND | -0.3 | 0.3 | V | 2 | |||
| LX Total RMS Current | -4 | 4 | A | 2 | |||
| Junction Temperature | 150 | ºC | 2 | ||||
| Storage Temperature Range | -65 | 160 | ºC | 2 | |||
| Lead Temperature (soldering, 10s) | 300 | ºC | soldering, 10s | 2 | |||
| Soldering Temperature (reflow) | 260 | ºC | reflow | 2 | |||
| Ambient Operating Temperature Range | TA | -40 | 125 | ºC | High industrial ambient range (features) | 1 | |
| Input Voltage Range | VIN | 4.5 | 60 | V | 2 | ||
| Input Shutdown Current | IIN-SH | 2.8 | 4.5 | µA | VEN/UVLO = 0V (shutdown mode) | 2 | |
| Input Quiescent Current (DCM) | IQ-DCM | 1.16 | 1.8 | mA | DCM mode, VLX = 0.1V | 2 | |
| EN/UVLO Threshold rising | VENR | 1.19 | 1.215 | 1.26 | V | VEN/UVLO rising | 3 |
| EN/UVLO Threshold falling | VENF | 1.068 | 1.09 | 1.131 | V | VEN/UVLO falling | 3 |
| EN/UVLO Input Leakage Current | IEN | -50 | 0 | 50 | nA | VEN/UVLO = 0V, TA = +25ºC | 3 |
| VCC Output Voltage Range | VCC | 4.75 | 5 | 5.25 | V | 6V < VIN < 60V, IVCC = 1mA | 3 |
| VCC Current Limit | IVCC-MAX | 26.5 | 54 | 100 | mA | VCC = 4.3V, VIN = 6V | 3 |
| VCC UVLO rising | VCC_UVR | 4.05 | 4.2 | 4.3 | V | VCC rising | 3 |
| VCC UVLO falling | VCC_UVF | 3.65 | 3.8 | 3.9 | V | VCC falling | 3 |
| High-Side nMOS On-Resistance | RDS-ONH | 165 | 325 | mΩ | ILX = 0.3A | 3 | |
| Low-Side nMOS On-Resistance | RDS-ONL | 80 | 150 | mΩ | ILX = 0.3A | 3 | |
| LX Leakage Current | ILX_LKG | -2 | 2 | µA | VLX = VIN - 1V, VLX = VPGND + 1V, TA = +25ºC | 3 | |
| Soft-Start Charging Current | ISS | 4.7 | 5 | 5.3 | µA | VSS = 0.5V | 3 |
| FB Regulation Voltage | VFB_REG | 0.89 | 0.9 | 0.91 | V | -40ºC ≤ TA ≤ +125ºC | 3 |
| FB Input Bias Current | IFB | -50 | 50 | nA | 0 < VFB < 1V, TA = +25ºC | 3 | |
| FB Threshold for Entering Hibernate Mode | VFB_HBR | 100.8 | 102.3 | 103.5 | % | VFB rising | 3 |
| FB Threshold for Exiting Hibernate Mode | VFB_HBF | 100 | 101.1 | 102.3 | % | VFB falling | 3 |
| Peak Current-Limit Threshold | IPEAK-LIMIT | 3.2 | 3.7 | 4.3 | A | 3 | |
| Runaway Current-Limit Threshold | IRUNAWAY-LIMIT | 3.7 | 4.3 | 5 | A | 3 | |
| Valley Current-Limit Threshold | ISINK-LIMIT | -0.16 | 0 | 0.16 | A | MODE = open/VCC | 3 |
| Valley Current-Limit Threshold | ISINK-LIMIT | -1.8 | A | MODE = GND | 3 | ||
| PFM Current-Limit Threshold | IPFM | 0.6 | 0.75 | 0.9 | A | MODE = open | 3 |
| Switching Frequency | fSW | 90 | 100 | 110 | kHz | RRT = 210kΩ | 4 |
| Switching Frequency | fSW | 180 | 200 | 220 | kHz | RRT = 102kΩ | 4 |
| Switching Frequency | fSW | 475 | 500 | 525 | kHz | RRT = 40.2kΩ | 4 |
| Switching Frequency | fSW | 1950 | 2200 | 2450 | kHz | RRT = 8.06kΩ | 4 |
| Switching Frequency | fSW | 460 | 500 | 540 | kHz | RRT = open | 4 |
| SYNC Pulse Width | 50 | ns | minimum clock pulse-width high (text) | 4 | |||
| SYNC Threshold high | VIH | 2.1 | V | 4 | |||
| SYNC Threshold low | VIL | 0.8 | V | 4 | |||
| FB Undervoltage Trip Level to Cause Hiccup | VFB-HICF | 0.56 | 0.58 | 0.65 | V | 4 | |
| Minimum On-Time (MAX17503) | tON-MIN | 135 | ns | MAX17503 (not S) variant | 4 | ||
| Minimum Off-Time | tOFF-MIN | 140 | 160 | ns | 4 | ||
| RESET Output Level Low | 0.4 | V | IRESET = 10mA | 4 | |||
| RESET Output Leakage Current | -0.1 | 0.1 | µA | TA = TJ = +25ºC, VRESET = 5.5V | 4 | ||
| FB Threshold for RESET Assertion | VFB-OKF | 90.5 | 92 | 94.6 | %VFB-REG | VFB falling | 4 |
| FB Threshold for RESET Deassertion | VFB-OKR | 93.8 | 95 | 97.8 | %VFB-REG | VFB rising | 4 |
| Junction to Ambient Thermal Resistance | θJA | 33 | °C/W | four-layer board, JESD51-7 | 2 | ||
| Junction to Case Thermal Resistance | θJC | 2 | °C/W | four-layer board, JESD51-7 | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | Exposed pad. Connect to the SGND pin. Connect to a large copper plane below the IC to improve heat | 16 |
CAD (KiCad official)
- Symbol:
MAX17503ATP+T - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: TQFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
max17503atp-t-etched.step/max17503atp-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max17503atp-t.step/max17503atp-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (27 pp, sha256
67d45e7c35519621, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).