# MAX17502EATB+T

**Analog Devices Inc Maxim Integrated** · Global Sourcing Parts · TDFN-10-EP(2x3)

MAX17502EATB+T from Analog Devices Inc Maxim Integrated, in a TDFN-10-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground for switching currents; connect externally to the power ground plane and tie GND and PGND together at the return of the VCC bypass capacitor. |
| 2 | VIN | power_in | Power-supply input with an operating range of 4.5V to 60V (VIN to GND absolute maximum is 70V). |
| 3 | EN/UVLO | input | Enable/undervoltage lockout input; drive high to enable the output, with a resistive divider from VIN setting the turn-on threshold (EN rising threshold 1.218V typ), and EN/UVLO is limited to -0.3V to (VIN + 0.3V). |
| 4 | VCC | power_out | 5V LDO output that must be bypassed with 1µF ceramic capacitance to GND; VCC is limited to -0.3V to +6V and the LDO can source up to 40mA (typ). |
| 5 | FB/VO | input | Feedback input; connect directly to the output for fixed 3.3V/5V versions or to the center of the resistive divider from VOUT to GND for adjustable versions, with FB limited to -0.3V to +6V. |
| 6 | SS | input | Soft-start input; connect a capacitor from SS to GND to set the soft-start time, with SS limited to -0.3V to +6V. |
| 7 | N.C./COMP | unconnected | For the fixed-output MAX17502E this pin is no connect and must be left unconnected; on adjustable MAX17502G/H it is the COMP external loop-compensation pin connected to an RC network to GND. |
| 8 | RESET | output | Open-drain reset output that goes low when FB falls below 92.5% of its set value and goes high 1024 clock cycles after FB rises above 95.5%; it requires an external pullup and can sink 2mA while low. |
| 9 | GND | power_in | Analog ground for the control circuitry; connect to the exposed pad and keep separate from PGND except at the VCC bypass capacitor return. |
| 10 | LX | output | Switching node connected to the switching side of the inductor; LX is high impedance in shutdown and LX total RMS current is rated ±1.6A. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | TDFN-10-EP(2x3) |
| Category | Global Sourcing Parts |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 |  | 60 | V |  | 2 |
| Input Supply Current, shutdown | IIN-SH |  | 0.9 | 3.5 | µA | VEN = 0V, shutdown mode | 2 |
| Input Supply Current, normal switching (MAX17502E/F/G) | IIN-SW | 4.75 |  | 6.75 | mA | Normal switching mode, no load | 2 |
| EN Threshold, rising | VENR | 1.194 | 1.218 | 1.236 | V | VEN rising | 2 |
| EN Threshold, falling | VENF | 1.114 | 1.135 | 1.156 | V | VEN falling | 2 |
| EN True Shutdown Threshold | VEN-TRUESD |  |  | 0.7 | V | VEN falling, true shutdown | 2 |
| EN Input Leakage Current | IEN |  | 8 | 200 | nA | VEN = VIN = 60V, TA = +25°C | 2 |
| VCC Output Voltage Range | VCC | 4.65 | 5 | 5.35 | V | 6V < VIN < 12V, 0mA < IVCC < 10mA; 12V < VIN < 60V, 0mA < IVCC < 2mA | 2 |
| VCC Current Limit | IVCC-MAX | 15 | 40 | 80 | mA | VCC = 4.3V, VIN = 12V | 2 |
| VCC Dropout | VCC-DO |  |  | 4.1 | V | VIN = 4.5V, IVCC = 5mA | 2 |
| VCC UVLO rising | VCC-UVR | 3.85 | 4 | 4.15 | V | VCC rising | 2 |
| VCC UVLO falling | VCC-UVF | 3.55 | 3.7 | 3.85 | V | VCC falling | 2 |
| High-Side pMOS On-Resistance | RDS-ONH |  | 0.55 | 0.85 | Ω | ILX = 0.5A (sourcing), TA = +25°C | 3 |
| High-Side pMOS On-Resistance at high temperature | RDS-ONH |  |  | 1.2 | Ω | ILX = 0.5A (sourcing), TA = TJ = +125°C (guaranteed by design, not production tested) | 3 |
| Low-Side nMOS On-Resistance | RDS-ONL |  | 0.2 | 0.35 | Ω | ILX = 0.5A (sinking), TA = +25°C | 3 |
| Low-Side nMOS On-Resistance at high temperature | RDS-ONL |  |  | 0.47 | Ω | ILX = 0.5A (sinking), TA = TJ = +125°C (guaranteed by design, not production tested) | 3 |
| LX Leakage Current | ILX_LKG |  |  | 1 | µA | VEN = 0V, TA = +25°C, VLX = (VPGND + 1V) to (VIN - 1V) | 3 |
| Soft-Start Charging Current | ISS | 4.7 | 5 | 5.3 | µA | VSS = 0.5V | 3 |
| FB Input Bias Current (MAX17502E) | IFB | 6.8 | 12 | 17 | µA | TA = +25°C, MAX17502E, VFB = 3.3V | 3 |
| Output Voltage (MAX17502E, 3.3V fixed) | VOUT | 3.248 | 3.3 | 3.352 | V | MAX17502E | 3 |
| Peak Current-Limit Threshold | IPEAK-LIMIT | 1.4 | 1.65 | 1.9 | A |  | 4 |
| Runaway Current-Limit Threshold | IRUNAWAY-LIMIT | 1.45 | 1.7 | 2 | A |  | 4 |
| Sink Current-Limit Threshold | ISINK-LIMIT | 0.56 | 0.65 | 0.74 | A | MAX17502E/F/G/H | 4 |
| Switching Frequency (MAX17502E) | fSW | 560 | 600 | 640 | kHz | VFB > VOUT-HICF | 4 |
| Switching Frequency during foldback | fSW | 280 | 300 | 320 | kHz | VFB < VOUT-HICF | 4 |
| VOUT Undervoltage Trip Level to Cause Hiccup | VOUT-HICF | 69.14 | 71.14 | 73.14 | % | VSS > 0.95V (soft-start is done) | 4 |
| Minimum On-Time | tON_MIN |  | 75 | 120 | ns |  | 4 |
| Maximum Duty Cycle (MAX17502E) | DMAX | 92 | 94 | 96 | % | VFB = 0.98 x VFB-REG | 4 |
| RESET Output Level Low |  |  |  | 0.02 | V | IRESET = 1mA | 4 |
| RESET Output Leakage Current, high |  |  |  | 0.45 | µA | VFB = 1.01 x VFB-REG, TA = +25°C | 4 |
| VOUT Threshold for RESET Falling | VOUT-OKF | 90.5 | 92.5 | 94.5 | % | VFB falling | 4 |
| VOUT Threshold for RESET Rising | VOUT-OKR | 93.5 | 95.5 | 97.5 | % | VFB rising | 4 |
| Thermal-Shutdown Threshold |  |  | 165 |  | °C | Temperature rising | 4 |
| Thermal-Shutdown Hysteresis |  |  | 10 |  | °C |  | 4 |
| VIN to GND |  | -0.3 |  | 70 | V |  | 2 |
| EN/UVLO to GND (absolute max is VIN + 0.3V, not numeric) |  | -0.3 |  |  | V |  | 2 |
| LX to PGND (absolute max is VIN + 0.3V, not numeric) |  | -0.3 |  |  | V |  | 2 |
| FB, RESET, COMP, SS to GND |  | -0.3 |  | 6 | V |  | 2 |
| VCC to GND |  | -0.3 |  | 6 | V |  | 2 |
| GND to PGND |  | -0.3 |  | 0.3 | V |  | 2 |
| LX Total RMS Current |  | -1.6 |  | 1.6 | A |  | 2 |
| Junction Temperature |  |  |  | 150 | °C |  | 2 |
| Storage Temperature Range |  | -65 |  | 160 | °C |  | 2 |
| Lead Temperature (soldering, 10s) |  |  |  | 300 | °C | Soldering, 10s | 2 |
| Soldering Temperature (reflow) |  |  |  | 260 | °C | Reflow | 2 |
| Derating above +70°C (10 TDFN) |  |  | 14.9 |  | mW/°C | Above TA = +70°C, multilayer board | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  |, EP Exposed Pad. Connect to the GND pin of the IC. Connect to a large copper plane below the IC | 9 |

## CAD (KiCad official)

- Symbol: `MAX17502EATB+T`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_2x3mm_P0.5mm_EP0.64x2.4mm`
- 3D model: TDFN-10-EP(2x3) (KiCad packages3D, STEP)
- 3D model files: `max17502eatb-t-etched.step` / `max17502eatb-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `max17502eatb-t.step` / `max17502eatb-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices Inc Maxim Integrated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886679364624384) (21 pp, sha256 `a4385054b0b515b7`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/max17502eatb-t-datasheet.pdf)