component
MAX17501FATB+T
Public Made by Adomby adom
Maxim Integrated DC-DC Converters, TDFN-10-EP(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownMAX17501FATB+T
Maxim Integrated · DC-DC Converters · TDFN-10-EP(2x3)
MAX17501FATB+T from Maxim Integrated, in a TDFN-10-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground; connect externally to the power ground plane and tie GND and PGND together at the ground return of the VCC bypass capacitor. |
| 2 | VIN | power_in | Power-supply input with an input supply range of 4.5V to 60V. |
| 3 | EN/UVLO | input | Enable/undervoltage lockout input: drive high to enable the output, set the input turn-on threshold with a resistive divider from VIN to GND, or pull up to VIN for always on. |
| 4 | VCC | power_out | 5V LDO output that must be bypassed to GND with 1µF ceramic capacitance. |
| 5 | FB/VO | input | Feedback input: connect directly to the output for fixed-output versions, or to the center of a resistive divider between VOUT and GND for adjustable versions. |
| 6 | SS | input | Soft-start input; a capacitor from SS to GND sets the soft-start time. |
| 7 | N.C./COMP | unconnected | For the fixed-output MAX17501F this pin is a no connect and must be left unconnected; on the adjustable MAX17501G/H it is the COMP pin for an RC compensation network to GND. |
| 8 | RESET | output | Open-drain power-good output that is driven low if FB drops below 92.5% of its set value and goes high 1024 clock cycles after FB rises above 95.5%, valid when the device is enabled and VIN is above 4.5V. |
| 9 | GND | power_in | Analog ground for the device. |
| 10 | LX | output | Switching node connected to the inductor; high impedance when the device is in shutdown. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Maxim Integrated |
| Package | TDFN-10-EP(2x3) |
| Category | Power Management ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | 60 | V | 2 | ||
| Input Supply Current, shutdown | IIN-SH | 0.9 | 3.5 | µA | VEN = 0V, shutdown mode | 2 | |
| Input Supply Current, normal switching | IIN-SW | 4.75 | 6.75 | mA | Normal switching mode, no load (MAX17501E/F/G) | 2 | |
| EN Threshold rising | VENR | 1.194 | 1.218 | 1.236 | V | VEN rising | 2 |
| EN Threshold falling | VENF | 1.114 | 1.135 | 1.156 | V | VEN falling | 2 |
| EN Threshold true shutdown | VEN-TRUESD | 0.7 | V | VEN falling, true shutdown | 2 | ||
| EN Input Leakage Current | IEN | 8 | 200 | nA | VEN = VIN = 60V, TA = +25°C | 2 | |
| VCC Output Voltage Range | VCC | 4.65 | 5 | 5.35 | V | 6V < VIN < 12V, 0mA < IVCC < 10mA, 12V < VIN < 60V, 0mA < IVCC < 2mA | 2 |
| VCC Current Limit | IVCC-MAX | 15 | 40 | 80 | mA | VCC = 4.3V, VIN = 12V | 2 |
| VCC Dropout | VCC-DO | 4.1 | V | VIN = 4.5V, IVCC = 5mA | 2 | ||
| VCC UVLO rising | VCC-UVR | 3.85 | 4 | 4.15 | V | VCC rising | 2 |
| VCC UVLO falling | VCC-UVF | 3.55 | 3.7 | 3.85 | V | VCC falling | 2 |
| High-Side pMOS On-Resistance | RDS-ONH | 0.55 | 0.85 | Ω | ILX = 0.5A (sourcing), TA = +25°C | 3 | |
| High-Side pMOS On-Resistance | RDS-ONH | 1.2 | Ω | ILX = 0.5A (sourcing), TA = TJ = +125°C (Note 3) | 3 | ||
| Low-Side nMOS On-Resistance | RDS-ONL | 0.2 | 0.35 | Ω | ILX = 0.5A (sinking), TA = +25°C | 3 | |
| Low-Side nMOS On-Resistance | RDS-ONL | 0.47 | Ω | ILX = 0.5A (sinking), TA = TJ = +125°C (Note 3) | 3 | ||
| LX Leakage Current | ILX_LKG | 1 | µA | VEN = 0V, TA = +25°C, VLX = (VPGND + 1V) to (VIN - 1V) | 3 | ||
| Soft-Start Charging Current | ISS | 4.7 | 5 | 5.3 | µA | VSS = 0.5V | 3 |
| FB Input Bias Current | IFB | 6.8 | 12 | 17 | µA | TA = +25°C, MAX17501B/F, VFB = 5V | 3 |
| Output Voltage Accuracy (MAX17501F, 5V output) | VOUT | 4.922 | 5 | 5.08 | V | 3 | |
| Peak Current-Limit Threshold | IPEAK-LIMIT | 0.64 | 0.76 | 0.86 | A | 3 | |
| Runaway Current-Limit Threshold | IRUNAWAY-LIMIT | 0.65 | 0.78 | 0.905 | A | 3 | |
| Sink Current-Limit Threshold | ISINK-LIMIT | 0.3 | 0.35 | 0.4 | A | MAX17501E/F/G/H | 3 |
| Switching Frequency | fSW | 560 | 600 | 640 | kHz | VFB > VOUT-HICF (MAX17501A/B/E/F/G) | 4 |
| Switching Frequency (foldback) | fSW | 280 | 300 | 320 | kHz | VFB < VOUT-HICF | 4 |
| VOUT Undervoltage Trip Level to Cause Hiccup | VOUT-HICF | 69.14 | 71.14 | 73.14 | % | VSS > 0.95V (soft-start is done) | 4 |
| Minimum On-Time | tON_MIN | 75 | 120 | ns | 4 | ||
| Maximum Duty Cycle | DMAX | 92 | 94 | 96 | % | VFB = 0.98 x VFB-REG (MAX17501A/B/E/F/G) | 4 |
| RESET Output Level Low | 0.02 | V | IRESET = 1mA | 4 | |||
| RESET Output Leakage Current High | 0.45 | µA | VFB = 1.01 x VFB-REG, TA = +25°C | 4 | |||
| VOUT Threshold for RESET Falling | VOUT-OKF | 90.5 | 92.5 | 94.5 | % | VFB falling | 4 |
| VOUT Threshold for RESET Rising | VOUT-OKR | 93.5 | 95.5 | 97.5 | % | VFB rising | 4 |
| Input Voltage to GND (absolute maximum) | VIN | -0.3 | 70 | V | VIN to GND | 2 | |
| EN/UVLO to GND (absolute maximum) | EN/UVLO | -0.3 | V | EN/UVLO to GND; upper limit printed as (VIN + 0.3V) | 2 | ||
| LX to PGND (absolute maximum) | LX | -0.3 | V | LX to PGND; upper limit printed as (VIN + 0.3V) | 2 | ||
| FB, RESET, COMP, SS to GND (absolute maximum) | FB, RESET, COMP, SS | -0.3 | 6 | V | to GND | 2 | |
| VCC to GND (absolute maximum) | VCC | -0.3 | 6 | V | to GND | 2 | |
| GND to PGND (absolute maximum) | GND-PGND | -0.3 | 0.3 | V | 2 | ||
| LX Total RMS Current (absolute maximum) | ILX | -1.6 | 1.6 | A | LX total RMS current | 2 | |
| Junction Temperature (absolute maximum) | TJ | 150 | °C | 2 | |||
| Storage Temperature Range (absolute maximum) | TSTG | -65 | 160 | °C | 2 | ||
| Lead Temperature (absolute maximum) | 300 | °C | soldering, 10s | 2 | |||
| Soldering Temperature, reflow (absolute maximum) | 260 | °C | reflow | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | , EP Exposed Pad. Connect to the GND pin of the IC. Connect to a large copper plane below the IC to improve | 11 |
CAD (KiCad official)
- Symbol:
MAX17501FATB+T - Footprint:
Package_DFN_QFN:DFN-10-1EP_2x3mm_P0.5mm_EP0.64x2.4mm - 3D model: TDFN-10-EP(2x3) (KiCad packages3D, STEP)
- 3D model files:
max17501fatb-t-etched.step/max17501fatb-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max17501fatb-t.step/max17501fatb-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Maxim Integrated datasheet (22 pp, sha256
23ebc68b9b2a59dd, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).