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MAX17320G22+
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Analog Devices Inc Maxim Integrated Battery Management, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MAX17320G22+
Analog Devices Inc Maxim Integrated · Battery Management · QFN-24-EP(4x4)
MAX17320G22+ from Analog Devices Inc Maxim Integrated, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power supply input connected to the positive terminal of the cell stack through a 10Ω resistor, bypassed with a 0.1µF/25V ceramic capacitor to GND. |
| 2 | CP | power_out | Charge pump output and bypass, bypassed to IN with a 0.47µF/25V ceramic capacitor. |
| 3 | CHG | output | Charge FET gate control that enables or disables the high-side CHG N-FET by driving its gate between CP and IN, with a 0.1µF capacitor from gate to source. |
| 4 | DIS | output | Discharge FET gate control that enables or disables the high-side DIS N-FET by driving its gate between CP and PCKP. |
| 5 | ZVC | passive | Zero-volt charge path where the recovery charge current is set by the resistor from PCKP to ZVC, and it is left open if not used. |
| 6 | PCKP | passive | Connects to the positive terminal of the pack connector through 1kΩ. |
| 7 | ALRT | output | Programmable alert output. |
| 8 | SCL/OD | input | Input-only serial clock for I2C communication or speed selection for 1-Wire communication, with an internal pulldown used for sensing pack disconnection. |
| 9 | SDA/DQ | bidirectional | Open-drain serial data input/output for both 1-Wire and I2C modes, connected to the DATA terminal of the battery pack, with an internal pulldown used for sensing pack disconnection. |
| 10 | TH1 | passive | Thermistor input 1 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 11 | PFAIL | output | Permanent failure indicator connected to a three-terminal fuse for primary FET failure action; if not used, connect to GND through a 1kΩ resistor. |
| 12 | AOLDO | power_out | Always-on LDO configurable as 3.4V or 1.8V, bypassed to GND with a 0.47µF/10V ceramic capacitor, or connected to GND with a 10kΩ resistor if not used. |
| 13 | REG3 | power_out | Internal 3.4V regulator output bypassed to GND with a 0.47µF/10V ceramic capacitor. |
| 14 | CSN | power_in | System ground and current-measurement negative sense point, Kelvin-connected to the load side of the sense resistor. |
| 15 | CSP | power_in | Device ground and current-measurement positive sense point, Kelvin-connected to the cell side of the sense resistor. |
| 16 | TH2 | passive | Thermistor input 2 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 17 | REG2 | power_out | Internal 1.8V regulator output bypassed to GND with a 0.47µF/10V ceramic capacitor. |
| 18 | TH3 | passive | Thermistor input 3 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 19 | TH4 | passive | Thermistor input 4 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 20 | GND | power_in | Ground pin that must connect to ground and must not share the ground trace with the CSP Kelvin-sense trace. |
| 21 | CELL1 | passive | Cell voltage sense 1 used for cell balancing and voltage sensing. |
| 22 | CELL2 | passive | Cell voltage sense 2 used for cell balancing and voltage sensing. |
| 23 | CELL3 | passive | Cell voltage sense 3 used for cell balancing and voltage sensing. |
| 24 | BATTS | passive | Battery voltage sense of the top cell in the series stack, used for cell balancing and voltage sensing. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | QFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | 4.2 | 18 | V | 21 | ||
| Shutdown Supply Current | IDD0 | 2.2 | 3.5 | μA | Shutdown, VBATT = 18V, +25°C | 21 | |
| Ship Mode Supply Current | IDD1 | 16 | 25 | μA | TA ≤ +50°C | 21 | |
| Active Supply Current | IDD2 | 38 | 57 | μA | TA ≤ +50°C, average current, not including thermistor measurement current, AOLDO off | 21 | |
| Always-On LDO Voltage (1.8V output) | VAOLDO | 1.62 | 1.8 | 1.98 | V | 1.8V output, ILOAD = 2mA | 21 |
| Always-On LDO Voltage (3.4V output) | VAOLDO | 3 | 3.4 | 3.8 | V | 3.4V output, ILOAD = 2mA | 21 |
| Charge Pump Output (6V selection) | VCP | 5 | 6 | 7 | V | 6V selection | 21 |
| Charge Pump Output (8V setting) | VCP | 7 | 8 | 9 | V | 8V setting, VIN > 6V | 21 |
| Charge Pump Output (10V setting) | VCP | 9 | 10 | 11 | V | 10V setting, VIN > 7.5V | 21 |
| ZVC Minimum Voltage (10mA recovery current) | VZVCMIN | 1.4 | 2.4 | 3.3 | V | IN = 0, 10mA recovery current | 21 |
| ZVC Minimum Voltage (30mA recovery current) | VZVCMIN | 2.1 | 2.9 | 3.8 | V | IN = 0, 30mA recovery current | 21 |
| ZVC Minimum Voltage (50mA recovery current) | VZVCMIN | 2.5 | 3.4 | 4.5 | V | IN = 0, 50mA recovery current | 21 |
| Cell Voltage Measurement Error | VGERR | -12.5 | 12.5 | mV | TA = +25°C (Note 10) | 21 | |
| Cell Voltage Measurement Error | VGERR | -25 | 25 | mV | (Note 10) | 21 | |
| Cell Voltage Mismatch Error | VCMM | -5 | 5 | mV | Cell voltage mismatch between channels (CELL1, 2, 3, 4), +25°C | 22 | |
| BATT Voltage Measurement Error | VBGERR | -30 | 30 | mV | TA = +25°C, IN = BATTS, from 4.2V to 20V | 22 | |
| BATT Voltage Measurement Error | VBGERR | -100 | 100 | mV | IN = BATTS, from 4.2V to 20V | 22 | |
| PCKP Voltage Measurement Error | VPGERR | -30 | 30 | mV | TA = +25°C | 22 | |
| PCKP Voltage Measurement Error | VPGERR | -100 | 100 | mV | 22 | ||
| Cell Voltage Measurement Range | VFS | 2.1 | 4.9 | V | (Note 10) | 22 | |
| BATT Voltage Measurement Range | VBFS | 4.2 | 19.6 | V | BATTS pin | 22 | |
| PCKP Voltage Measurement Range | VPFS | 4.2 | 19.6 | V | PCKP pin | 22 | |
| Current Measurement Offset Error | IOERR | -2 | 2 | μV | CSP = 0V, long-term average (Note 2) | 22 | |
| Current Measurement Gain Error | IGERR | -1 | 1 | % of Reading | CSP between -50mV and +50mV | 22 | |
| Current Measurement Range | IFS | -51.2 | 51.2 | mV | 22 | ||
| Die Temperature Measurement Error | TIGERR | -1 | 1 | ºC | 22 | ||
| Thermistor Measurement Error | TEGERR | -1 | 1 | % of Reading | See the Thermistor Configuration section | 22 | |
| Leakage Current (CELL1, CELL2, CELL3, BATTS, CSN, ALRT, PFAIL, ZVC, CHG, DIS) | ILEAK | -1 | 1 | μA | ALRT < 15V, IN < CP < 30V | 22 | |
| Cell-Balancing Resistance | RBAL | 3 | 9 | 20 | Ω | VBATT = 18V, IBAL = 50mA, between BATTS - CELL3, CELL3 - CELL2, CELL2 - CELL1, and CELL1 - CSP | 23 |
| Output Drive Low (ALRT, SDA/DQ, PFAIL) | VOL | 0.4 | V | IOL = 4mA, REG3 = 3.4V | 23 | ||
| Input Logic High (SCL/OD, SDA/DQ, ALRT) | VIH | 1.5 | V | 23 | |||
| Input Logic Low (SCL/OD, SDA/DQ, ALRT) | VIL | 0.44 | V | 23 | |||
| Overcurrent Threshold Offset Error | OCOE | -1.2 | 1.2 | mV | OC, OD, or SC comparator | 23 | |
| Overcurrent Threshold Gain Error | OCGE | -5 | 5 | % of Threshold | OC, OD, or SC comparator | 23 | |
| 1-Wire Time Slot (regular speed) | tSLOT | 60 | 120 | μs | 23 | ||
| 1-Wire Write-0 Low Time (regular speed) | tLOW0 | 60 | 120 | μs | 23 | ||
| 1-Wire Write-1 Low Time (regular speed) | tLOW1 | 1 | 15 | μs | 23 | ||
| Time-Base Accuracy | tERR | -1 | 1 | % | TA = +25°C | 25 | |
| IN to GND | -0.3 | 20 | V | 18 | |||
| BATTS to CELL3 (balancing switches) | -0.3 | 20 | V | 18 | |||
| CELL3 to CELL2 (balancing switches) | -0.3 | 20 | V | 18 | |||
| CELL2 to CELL1 (balancing switches) | -0.3 | 20 | V | 18 | |||
| CELL1 to GND (balancing switches) | -0.3 | 20 | V | 18 | |||
| CP to GND | -0.3 | 36 | V | 18 | |||
| CP to IN | -0.3 | 36 | V | 18 | |||
| PCKP, ZVC to GND | -0.3 | 28 | V | 18 | |||
| SCL, SDA, ALRT to GND | -0.3 | 20 | V | 18 | |||
| REG3, AOLDO to GND | -0.3 | 6 | V | 18 | |||
| REG2 to GND | -0.3 | 2.2 | V | 18 | |||
| CSN to GND | -2 | 2 | V | 18 | |||
| CSP to GND | -0.3 | 0.3 | V | 18 | |||
| Operating Temperature Range | -40 | 85 | °C | 18 | |||
| Thermal Resistance, Single-Layer Board, Junction to Ambient | θJA | 68 | °C/W | Single-layer board | 20 | ||
| Thermal Resistance, Single-Layer Board, Junction to Case | θJC | 11 | °C/W | Single-layer board | 20 | ||
| Thermal Resistance, Four-Layer Board, Junction to Ambient | θJA | 60 | °C/W | Four-layer board | 20 | ||
| Thermal Resistance, Four-Layer Board, Junction to Case | θJC | 11 | °C/W | Four-layer board | 20 |
CAD (KiCad official)
- Symbol:
MAX17320G22+ - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
max17320g22-etched.step/max17320g22-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max17320g22.step/max17320g22.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (179 pp, sha256
4c96fe0d8b1fe60d, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MAX17320G22+
**Analog Devices Inc Maxim Integrated** · Battery Management · QFN-24-EP(4x4)
MAX17320G22+ from Analog Devices Inc Maxim Integrated, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power supply input connected to the positive terminal of the cell stack through a 10Ω resistor, bypassed with a 0.1µF/25V ceramic capacitor to GND. |
| 2 | CP | power_out | Charge pump output and bypass, bypassed to IN with a 0.47µF/25V ceramic capacitor. |
| 3 | CHG | output | Charge FET gate control that enables or disables the high-side CHG N-FET by driving its gate between CP and IN, with a 0.1µF capacitor from gate to source. |
| 4 | DIS | output | Discharge FET gate control that enables or disables the high-side DIS N-FET by driving its gate between CP and PCKP. |
| 5 | ZVC | passive | Zero-volt charge path where the recovery charge current is set by the resistor from PCKP to ZVC, and it is left open if not used. |
| 6 | PCKP | passive | Connects to the positive terminal of the pack connector through 1kΩ. |
| 7 | ALRT | output | Programmable alert output. |
| 8 | SCL/OD | input | Input-only serial clock for I2C communication or speed selection for 1-Wire communication, with an internal pulldown used for sensing pack disconnection. |
| 9 | SDA/DQ | bidirectional | Open-drain serial data input/output for both 1-Wire and I2C modes, connected to the DATA terminal of the battery pack, with an internal pulldown used for sensing pack disconnection. |
| 10 | TH1 | passive | Thermistor input 1 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 11 | PFAIL | output | Permanent failure indicator connected to a three-terminal fuse for primary FET failure action; if not used, connect to GND through a 1kΩ resistor. |
| 12 | AOLDO | power_out | Always-on LDO configurable as 3.4V or 1.8V, bypassed to GND with a 0.47µF/10V ceramic capacitor, or connected to GND with a 10kΩ resistor if not used. |
| 13 | REG3 | power_out | Internal 3.4V regulator output bypassed to GND with a 0.47µF/10V ceramic capacitor. |
| 14 | CSN | power_in | System ground and current-measurement negative sense point, Kelvin-connected to the load side of the sense resistor. |
| 15 | CSP | power_in | Device ground and current-measurement positive sense point, Kelvin-connected to the cell side of the sense resistor. |
| 16 | TH2 | passive | Thermistor input 2 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 17 | REG2 | power_out | Internal 1.8V regulator output bypassed to GND with a 0.47µF/10V ceramic capacitor. |
| 18 | TH3 | passive | Thermistor input 3 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 19 | TH4 | passive | Thermistor input 4 for a 10k/100k thermistor connected to GND; leave disconnected or connect to GND if not used. |
| 20 | GND | power_in | Ground pin that must connect to ground and must not share the ground trace with the CSP Kelvin-sense trace. |
| 21 | CELL1 | passive | Cell voltage sense 1 used for cell balancing and voltage sensing. |
| 22 | CELL2 | passive | Cell voltage sense 2 used for cell balancing and voltage sensing. |
| 23 | CELL3 | passive | Cell voltage sense 3 used for cell balancing and voltage sensing. |
| 24 | BATTS | passive | Battery voltage sense of the top cell in the series stack, used for cell balancing and voltage sensing. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | QFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | 4.2 | | 18 | V | | 21 |
| Shutdown Supply Current | IDD0 | | 2.2 | 3.5 | μA | Shutdown, VBATT = 18V, +25°C | 21 |
| Ship Mode Supply Current | IDD1 | | 16 | 25 | μA | TA ≤ +50°C | 21 |
| Active Supply Current | IDD2 | | 38 | 57 | μA | TA ≤ +50°C, average current, not including thermistor measurement current, AOLDO off | 21 |
| Always-On LDO Voltage (1.8V output) | VAOLDO | 1.62 | 1.8 | 1.98 | V | 1.8V output, ILOAD = 2mA | 21 |
| Always-On LDO Voltage (3.4V output) | VAOLDO | 3 | 3.4 | 3.8 | V | 3.4V output, ILOAD = 2mA | 21 |
| Charge Pump Output (6V selection) | VCP | 5 | 6 | 7 | V | 6V selection | 21 |
| Charge Pump Output (8V setting) | VCP | 7 | 8 | 9 | V | 8V setting, VIN > 6V | 21 |
| Charge Pump Output (10V setting) | VCP | 9 | 10 | 11 | V | 10V setting, VIN > 7.5V | 21 |
| ZVC Minimum Voltage (10mA recovery current) | VZVCMIN | 1.4 | 2.4 | 3.3 | V | IN = 0, 10mA recovery current | 21 |
| ZVC Minimum Voltage (30mA recovery current) | VZVCMIN | 2.1 | 2.9 | 3.8 | V | IN = 0, 30mA recovery current | 21 |
| ZVC Minimum Voltage (50mA recovery current) | VZVCMIN | 2.5 | 3.4 | 4.5 | V | IN = 0, 50mA recovery current | 21 |
| Cell Voltage Measurement Error | VGERR | -12.5 | | 12.5 | mV | TA = +25°C (Note 10) | 21 |
| Cell Voltage Measurement Error | VGERR | -25 | | 25 | mV | (Note 10) | 21 |
| Cell Voltage Mismatch Error | VCMM | -5 | | 5 | mV | Cell voltage mismatch between channels (CELL1, 2, 3, 4), +25°C | 22 |
| BATT Voltage Measurement Error | VBGERR | -30 | | 30 | mV | TA = +25°C, IN = BATTS, from 4.2V to 20V | 22 |
| BATT Voltage Measurement Error | VBGERR | -100 | | 100 | mV | IN = BATTS, from 4.2V to 20V | 22 |
| PCKP Voltage Measurement Error | VPGERR | -30 | | 30 | mV | TA = +25°C | 22 |
| PCKP Voltage Measurement Error | VPGERR | -100 | | 100 | mV | | 22 |
| Cell Voltage Measurement Range | VFS | 2.1 | | 4.9 | V | (Note 10) | 22 |
| BATT Voltage Measurement Range | VBFS | 4.2 | | 19.6 | V | BATTS pin | 22 |
| PCKP Voltage Measurement Range | VPFS | 4.2 | | 19.6 | V | PCKP pin | 22 |
| Current Measurement Offset Error | IOERR | -2 | | 2 | μV | CSP = 0V, long-term average (Note 2) | 22 |
| Current Measurement Gain Error | IGERR | -1 | | 1 | % of Reading | CSP between -50mV and +50mV | 22 |
| Current Measurement Range | IFS | -51.2 | | 51.2 | mV | | 22 |
| Die Temperature Measurement Error | TIGERR | -1 | | 1 | ºC | | 22 |
| Thermistor Measurement Error | TEGERR | -1 | | 1 | % of Reading | See the Thermistor Configuration section | 22 |
| Leakage Current (CELL1, CELL2, CELL3, BATTS, CSN, ALRT, PFAIL, ZVC, CHG, DIS) | ILEAK | -1 | | 1 | μA | ALRT < 15V, IN < CP < 30V | 22 |
| Cell-Balancing Resistance | RBAL | 3 | 9 | 20 | Ω | VBATT = 18V, IBAL = 50mA, between BATTS - CELL3, CELL3 - CELL2, CELL2 - CELL1, and CELL1 - CSP | 23 |
| Output Drive Low (ALRT, SDA/DQ, PFAIL) | VOL | | | 0.4 | V | IOL = 4mA, REG3 = 3.4V | 23 |
| Input Logic High (SCL/OD, SDA/DQ, ALRT) | VIH | 1.5 | | | V | | 23 |
| Input Logic Low (SCL/OD, SDA/DQ, ALRT) | VIL | | | 0.44 | V | | 23 |
| Overcurrent Threshold Offset Error | OCOE | -1.2 | | 1.2 | mV | OC, OD, or SC comparator | 23 |
| Overcurrent Threshold Gain Error | OCGE | -5 | | 5 | % of Threshold | OC, OD, or SC comparator | 23 |
| 1-Wire Time Slot (regular speed) | tSLOT | 60 | | 120 | μs | | 23 |
| 1-Wire Write-0 Low Time (regular speed) | tLOW0 | 60 | | 120 | μs | | 23 |
| 1-Wire Write-1 Low Time (regular speed) | tLOW1 | 1 | | 15 | μs | | 23 |
| Time-Base Accuracy | tERR | -1 | | 1 | % | TA = +25°C | 25 |
| IN to GND | | -0.3 | | 20 | V | | 18 |
| BATTS to CELL3 (balancing switches) | | -0.3 | | 20 | V | | 18 |
| CELL3 to CELL2 (balancing switches) | | -0.3 | | 20 | V | | 18 |
| CELL2 to CELL1 (balancing switches) | | -0.3 | | 20 | V | | 18 |
| CELL1 to GND (balancing switches) | | -0.3 | | 20 | V | | 18 |
| CP to GND | | -0.3 | | 36 | V | | 18 |
| CP to IN | | -0.3 | | 36 | V | | 18 |
| PCKP, ZVC to GND | | -0.3 | | 28 | V | | 18 |
| SCL, SDA, ALRT to GND | | -0.3 | | 20 | V | | 18 |
| REG3, AOLDO to GND | | -0.3 | | 6 | V | | 18 |
| REG2 to GND | | -0.3 | | 2.2 | V | | 18 |
| CSN to GND | | -2 | | 2 | V | | 18 |
| CSP to GND | | -0.3 | | 0.3 | V | | 18 |
| Operating Temperature Range | | -40 | | 85 | °C | | 18 |
| Thermal Resistance, Single-Layer Board, Junction to Ambient | θJA | | 68 | | °C/W | Single-layer board | 20 |
| Thermal Resistance, Single-Layer Board, Junction to Case | θJC | | 11 | | °C/W | Single-layer board | 20 |
| Thermal Resistance, Four-Layer Board, Junction to Ambient | θJA | | 60 | | °C/W | Four-layer board | 20 |
| Thermal Resistance, Four-Layer Board, Junction to Case | θJC | | 11 | | °C/W | Four-layer board | 20 |
## CAD (KiCad official)
- Symbol: `MAX17320G22+`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `max17320g22-etched.step` / `max17320g22-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `max17320g22.step` / `max17320g22.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices Inc Maxim Integrated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588919950132056064) (179 pp, sha256 `4c96fe0d8b1fe60d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/max17320g22-datasheet.pdf)