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MAX17260SETD+

Maxim Integrated · Battery Management ICs · TDFN-14-EP(3x3)

MAX17260SETD+ from Maxim Integrated, in a TDFN-14-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TH passive Thermistor input: connect a thermistor from TH to GND, and connect TH to BATT if not used; TH also provides battery insertion/removal detection.
2 NC unconnected No connection.
3 NC unconnected No connection.
4 NC unconnected No connection.
5 NC unconnected No connection.
6 BATT power_in IC power supply and battery voltage sense input, connected to the positive cell terminal and bypassed with a 0.1µF capacitor to GND.
7 CSN input Sense resistor negative sense point: Kelvin connect to the system side for a low-side application or the cell side for a high-side application, as determined by measuring CSN voltage at start-up.
8 GND power_in IC ground.
9 CSPL input Low-side sense resistor positive sense point, Kelvin connected to the cell side of the sense resistor.
10 CSPH input High-side sense resistor positive sense point: Kelvin connect to the system side of an external high-side sense resistor, or tie to BATT for low-side sensing.
11 REG power_out Internal 1.8V regulator output, bypassed with an external 0.47µF capacitor to GND; do not load externally.
12 ALRT output Open-drain active-low alert output indicating fuel-gauge alerts; connect to GND if not used. Absolute maximum sink current is 20mA and ALRT to GND is rated -0.3V to +17V.
13 SDA bidirectional Serial data input/output for the 2-wire I2C interface, open-drain driver with an internal pulldown for disconnection sensing.
14 SCL input Serial clock input for the 2-wire interface, input only, with an internal pulldown for disconnection sensing.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Maxim Integrated
Package TDFN-14-EP(3x3)
Category Power Management ICs
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VBATT 2.3 4.9 V (Note 1) 7
Shutdown Supply Current IDD0 0.5 0.9 μA TA ≤ +50ºC 7
Hibernate Supply Current IDD1 5.1 12 μA TA ≤ +50ºC, average current 7
Active Supply Current IDD2 15 30 μA TA ≤ +50ºC, average current not including thermistor measurement current 7
BATT Measurement Error VGERR -7.5 7.5 mV TA = +25ºC 7
BATT Measurement Error VGERR -20 20 mV -40ºC ≤ TA ≤ +85ºC 7
BATT Measurement Range VFS 2.3 4.9 V 7
Current Measurement Offset Error IOERR -1.5 1.5 μV Long-term average without load current 7
Current Measurement Error IGERR -1 1 % of Reading 7
Current Measurement Range IFS -51.2 51.2 mV 7
Internal Temperature Measurement Error TIGERR -1 1 ºC -40ºC ≤ TA ≤ +85ºC 7
Output Drive Low, ALRT, SDA VOL 0.4 V IOL = 4mA, VBATT = 2.3V 7
Input Logic High, ALRT, SCL, SDA VIH 1.5 V 7
Input Logic Low, ALRT, SCL, SDA VIL 0.5 V 7
Battery-Detach Detection Threshold VDET 91 96.2 99 % Measured as a fraction of VBATT on TH rising 7
Leakage Current, CSN, ALRT ILEAK -1 1 μA VALRT < 15V 7
Input Pulldown Current IPD 0.05 0.2 0.4 μA VSDA = 0.4V, VSCL = 0.4V 8
SCL Clock Frequency fSCL 0 400 kHz (Note 2) 8
Data Hold Time tHD:DAT 0 0.9 μs (Note 4, Note 5) 8
Rise Time of Both SDA and SCL Signals tR 5 300 ns 8
Fall Time of Both SDA and SCL Signals tF 5 300 ns 8
Time-Base Accuracy tERR -1 1 % TA = +25°C 8
BATT to GND -0.3 6 V 6
ALRT to GND -0.3 17 V 6
REG to GND -0.3 2.2 V 6
TH to GND -0.3 V upper limit printed as VBATT + 0.3 V 6
CSN to GND -0.3 V upper limit printed as VBATT + 0.3 V 6
CSPL to GND -0.3 0.3 V 6
SDA, SCL to GND -0.3 6 V 6
Operating Temperature Range -40 85 ºC 6
Junction Temperature 150 ºC 6
Storage Temperature Range -55 125 ºC 6
Soldering Temperature (reflow) 260 ºC 6
Continuous Source Current for TH 1 mA 6
Continuous Sink Current for SDA, ALRT 20 mA 6
Lead Temperature (soldering 10s) 300 ºC 6
External Thermistance Resistance REXT10 10 kΩ Config.R100 = 0 7
External Thermistance Resistance REXT100 100 kΩ Config.R100 = 1 7
Junction to Ambient (θJA) θJA 54 ºC/W Single-layer board, TDFN 6
Junction to Case (θJC) θJC 8 ºC/W Single-layer board, TDFN 6
Junction to Ambient (θJA) θJA 41 ºC/W Four-layer board, TDFN 6

CAD (KiCad official)

  • Symbol: MAX17260SETD+
  • Footprint: Package_DFN_QFN:DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm
  • 3D model: TDFN-14-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: max17260setd-etched.step / max17260setd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max17260setd.step / max17260setd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Maxim Integrated datasheet (30 pp, sha256 bb3f45316b854507, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF