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MAX15062BATA+T
Public Made by Adomby adom
Analog Devices Inc Maxim Integrated Global Sourcing Parts, WDFN-8(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MAX15062BATA+T
Analog Devices Inc Maxim Integrated · Global Sourcing Parts · WDFN-8(2x2)
MAX15062BATA+T from Analog Devices Inc Maxim Integrated, in a WDFN-8(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Switching regulator power input, specified for a 4.5V to 60V input range; bypass VIN to GND with an X7R 1µF ceramic capacitor. |
| 2 | EN/UVLO | input | Active-high enable/undervoltage-detection input; pull to GND to disable the regulator output, connect to VIN for always-on operation, or use a resistor divider from VIN to program the turn-on input voltage. |
| 3 | VCC | power_out | Internal LDO power output that must be bypassed to GND with a minimum 1µF capacitor. |
| 4 | FB/VOUT | input | Feedback input; connect directly to the output for fixed-voltage versions, or to a resistor divider between VOUT and GND to set the adjustable output from 0.9V to 0.89 x VIN. |
| 5 | MODE | input | PFM/PWM mode selection input; connect to GND for fixed-frequency PWM operation, or leave unconnected for light-load PFM operation. |
| 6 | RESET | output | Open-drain reset output that must be pulled up to an external supply through a resistor; it goes low when the output drops below 92% of the nominal regulated voltage and goes high impedance 2ms after the output rises above 95% of regulation. |
| 7 | GND | power_in | Ground; connect to the power ground plane and join all circuit ground connections at a single point. |
| 8 | LX | output | Inductor connection to the switching side of the inductor; LX is high impedance when the device is in shutdown. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | WDFN-8(2x2) |
| Category | Global Sourcing Parts |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | 60 | V | 2 | ||
| Input Shutdown Current | IIN-SH | 2.2 | 4 | µA | VEN/UVLO = 0V, shutdown mode | 2 | |
| Input Supply Current (PFM) | IQ-PFM | 95 | 160 | µA | MODE = unconnected, FB/VOUT = 1.03 x FB/VOUT-REG | 2 | |
| Input Supply Current (PWM) | IQ-PWM | 2.5 | 4 | mA | Normal switching mode, VIN = 24V | 2 | |
| EN/UVLO Threshold, rising | VENR | 1.19 | 1.215 | 1.24 | V | VEN/UVLO rising | 2 |
| EN/UVLO Threshold, falling | VENF | 1.06 | 1.09 | 1.15 | V | VEN/UVLO falling | 2 |
| EN/UVLO True Shutdown Threshold | VEN-TRUESD | 0.75 | V | VEN/UVLO falling, true shutdown | 2 | ||
| EN/UVLO Input Leakage Current | IEN/UVLO | -100 | 100 | nA | VEN/UVLO = 60V, TA = +25°C | 2 | |
| VCC Output Voltage Range | VCC | 4.75 | 5 | 5.25 | V | 6V < VIN < 60V, 0mA < IVCC < 10mA | 2 |
| VCC Current Limit | IVCC-MAX | 13 | 30 | 50 | mA | VCC = 4.3V, VIN = 12V | 2 |
| VCC Dropout | VCC-DO | 0.15 | 0.3 | V | VIN = 4.5V, IVCC = 5mA | 2 | |
| VCC UVLO Rising | VCC-UVR | 4.05 | 4.18 | 4.3 | V | VCC rising | 2 |
| VCC UVLO Falling | VCC-UVF | 3.7 | 3.8 | 3.95 | V | VCC falling | 2 |
| High-Side pMOS On-Resistance | RDS-ONH | 1.35 | 1.75 | Ω | ILX = 0.3A (sourcing), TA = +25°C | 3 | |
| High-Side pMOS On-Resistance at high temperature | RDS-ONH | 2.7 | Ω | ILX = 0.3A (sourcing), TA = TJ = +125°C | 3 | ||
| Low-Side nMOS On-Resistance | RDS-ONL | 0.45 | 0.55 | Ω | ILX = 0.3A (sinking), TA = +25°C | 3 | |
| Low-Side nMOS On-Resistance at high temperature | RDS-ONL | 0.9 | Ω | ILX = 0.3A (sinking), TA = TJ = +125°C | 3 | ||
| LX Leakage Current | ILX-LKG | -1 | 1 | µA | VEN/UVLO = 0V, VIN = 60V, TA = +25°C, VLX = (VGND + 1V) to (VIN - 1V) | 3 | |
| Soft-Start Time | tSS | 3.8 | 4.1 | 4.4 | ms | 3 | |
| VOUT Regulation Voltage (MAX15062B) | VOUT-REG | 4.93 | 5 | 5.07 | V | MODE = GND, MAX15062B | 3 |
| VOUT Regulation Voltage (MAX15062B) | VOUT-REG | 4.93 | 5.08 | 5.18 | V | MODE = unconnected, MAX15062B | 3 |
| Peak Current-Limit Threshold | IPEAK-LIMIT | 0.49 | 0.56 | 0.62 | A | 3 | |
| Runaway Current-Limit Threshold | IRUNAWAY-LIMIT | 0.58 | 0.66 | 0.73 | A | 3 | |
| Negative Current-Limit Threshold | ISINK-LIMIT | 0.25 | 0.3 | 0.35 | A | MODE = GND | 3 |
| Switching Frequency | fSW | 465 | 500 | 535 | kHz | 3 | |
| FB/VOUT Undervoltage Trip Level to Cause Hiccup | 62.5 | 64.5 | 66.5 | % | 3 | ||
| Minimum On-Time | tON-MIN | 90 | 130 | ns | 3 | ||
| Maximum Duty Cycle | DMAX | 89 | 91.5 | 94 | % | FB/VOUT = 0.98 x FB/VOUT-REG | 3 |
| RESET Threshold, rising | 93.5 | 95.5 | 97.5 | % | FB/VOUT rising | 4 | |
| RESET Threshold, falling | 90 | 92 | 94 | % | FB/VOUT falling | 4 | |
| RESET Output Level Low | 0.2 | V | IRESET = 5mA | 4 | |||
| RESET Output Leakage Current | 0.1 | µA | VRESET = 5.5V, TA = +25°C | 4 | |||
| VIN to GND (absolute maximum) | -0.3 | 70 | V | 2 | |||
| EN/UVLO to GND (absolute maximum) | -0.3 | 70 | V | 2 | |||
| LX to GND (absolute maximum) | -0.3 | V | maximum is VIN + 0.3V | 2 | |||
| VCC, FB/VOUT, RESET to GND (absolute maximum) | -0.3 | 6 | V | 2 | |||
| MODE to GND (absolute maximum) | -0.3 | V | maximum is VCC + 0.3V | 2 | |||
| LX Total RMS Current | -800 | 800 | mA | 2 | |||
| Junction Temperature | 150 | °C | 2 | ||||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Soldering Temperature (reflow) | 260 | °C | 2 | ||||
| Lead Temperature (soldering, 10s) | 300 | °C | 10s | 2 | |||
| Junction-to-Ambient Thermal Resistance | θJA | 162 | °C/W | TDFN, JESD51-7 four-layer board | 2 | ||
| Junction-to-Case Thermal Resistance | θJC | 20 | °C/W | TDFN | 2 | ||
| Operating Ambient Temperature Range | TA | -40 | 125 | °C | 1 | ||
| Operating Junction Temperature Range | TJ | -40 | 150 | °C | 1 |
CAD (KiCad official)
- Symbol:
MAX15062BATA+T - Footprint:
Package_DFN_QFN:WDFN-8-1EP_2x2mm_P0.5mm_EP0.8x1.2mm - 3D model: WDFN-8(2x2), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
max15062bata-t-etched.step/max15062bata-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max15062bata-t.step/max15062bata-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (23 pp, sha256
ffeeecba16f5442d, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MAX15062BATA+T
**Analog Devices Inc Maxim Integrated** · Global Sourcing Parts · WDFN-8(2x2)
MAX15062BATA+T from Analog Devices Inc Maxim Integrated, in a WDFN-8(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Switching regulator power input, specified for a 4.5V to 60V input range; bypass VIN to GND with an X7R 1µF ceramic capacitor. |
| 2 | EN/UVLO | input | Active-high enable/undervoltage-detection input; pull to GND to disable the regulator output, connect to VIN for always-on operation, or use a resistor divider from VIN to program the turn-on input voltage. |
| 3 | VCC | power_out | Internal LDO power output that must be bypassed to GND with a minimum 1µF capacitor. |
| 4 | FB/VOUT | input | Feedback input; connect directly to the output for fixed-voltage versions, or to a resistor divider between VOUT and GND to set the adjustable output from 0.9V to 0.89 x VIN. |
| 5 | MODE | input | PFM/PWM mode selection input; connect to GND for fixed-frequency PWM operation, or leave unconnected for light-load PFM operation. |
| 6 | RESET | output | Open-drain reset output that must be pulled up to an external supply through a resistor; it goes low when the output drops below 92% of the nominal regulated voltage and goes high impedance 2ms after the output rises above 95% of regulation. |
| 7 | GND | power_in | Ground; connect to the power ground plane and join all circuit ground connections at a single point. |
| 8 | LX | output | Inductor connection to the switching side of the inductor; LX is high impedance when the device is in shutdown. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | WDFN-8(2x2) |
| Category | Global Sourcing Parts |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | | 60 | V | | 2 |
| Input Shutdown Current | IIN-SH | | 2.2 | 4 | µA | VEN/UVLO = 0V, shutdown mode | 2 |
| Input Supply Current (PFM) | IQ-PFM | | 95 | 160 | µA | MODE = unconnected, FB/VOUT = 1.03 x FB/VOUT-REG | 2 |
| Input Supply Current (PWM) | IQ-PWM | | 2.5 | 4 | mA | Normal switching mode, VIN = 24V | 2 |
| EN/UVLO Threshold, rising | VENR | 1.19 | 1.215 | 1.24 | V | VEN/UVLO rising | 2 |
| EN/UVLO Threshold, falling | VENF | 1.06 | 1.09 | 1.15 | V | VEN/UVLO falling | 2 |
| EN/UVLO True Shutdown Threshold | VEN-TRUESD | | | 0.75 | V | VEN/UVLO falling, true shutdown | 2 |
| EN/UVLO Input Leakage Current | IEN/UVLO | -100 | | 100 | nA | VEN/UVLO = 60V, TA = +25°C | 2 |
| VCC Output Voltage Range | VCC | 4.75 | 5 | 5.25 | V | 6V < VIN < 60V, 0mA < IVCC < 10mA | 2 |
| VCC Current Limit | IVCC-MAX | 13 | 30 | 50 | mA | VCC = 4.3V, VIN = 12V | 2 |
| VCC Dropout | VCC-DO | | 0.15 | 0.3 | V | VIN = 4.5V, IVCC = 5mA | 2 |
| VCC UVLO Rising | VCC-UVR | 4.05 | 4.18 | 4.3 | V | VCC rising | 2 |
| VCC UVLO Falling | VCC-UVF | 3.7 | 3.8 | 3.95 | V | VCC falling | 2 |
| High-Side pMOS On-Resistance | RDS-ONH | | 1.35 | 1.75 | Ω | ILX = 0.3A (sourcing), TA = +25°C | 3 |
| High-Side pMOS On-Resistance at high temperature | RDS-ONH | | | 2.7 | Ω | ILX = 0.3A (sourcing), TA = TJ = +125°C | 3 |
| Low-Side nMOS On-Resistance | RDS-ONL | | 0.45 | 0.55 | Ω | ILX = 0.3A (sinking), TA = +25°C | 3 |
| Low-Side nMOS On-Resistance at high temperature | RDS-ONL | | | 0.9 | Ω | ILX = 0.3A (sinking), TA = TJ = +125°C | 3 |
| LX Leakage Current | ILX-LKG | -1 | | 1 | µA | VEN/UVLO = 0V, VIN = 60V, TA = +25°C, VLX = (VGND + 1V) to (VIN - 1V) | 3 |
| Soft-Start Time | tSS | 3.8 | 4.1 | 4.4 | ms | | 3 |
| VOUT Regulation Voltage (MAX15062B) | VOUT-REG | 4.93 | 5 | 5.07 | V | MODE = GND, MAX15062B | 3 |
| VOUT Regulation Voltage (MAX15062B) | VOUT-REG | 4.93 | 5.08 | 5.18 | V | MODE = unconnected, MAX15062B | 3 |
| Peak Current-Limit Threshold | IPEAK-LIMIT | 0.49 | 0.56 | 0.62 | A | | 3 |
| Runaway Current-Limit Threshold | IRUNAWAY-LIMIT | 0.58 | 0.66 | 0.73 | A | | 3 |
| Negative Current-Limit Threshold | ISINK-LIMIT | 0.25 | 0.3 | 0.35 | A | MODE = GND | 3 |
| Switching Frequency | fSW | 465 | 500 | 535 | kHz | | 3 |
| FB/VOUT Undervoltage Trip Level to Cause Hiccup | | 62.5 | 64.5 | 66.5 | % | | 3 |
| Minimum On-Time | tON-MIN | 90 | | 130 | ns | | 3 |
| Maximum Duty Cycle | DMAX | 89 | 91.5 | 94 | % | FB/VOUT = 0.98 x FB/VOUT-REG | 3 |
| RESET Threshold, rising | | 93.5 | 95.5 | 97.5 | % | FB/VOUT rising | 4 |
| RESET Threshold, falling | | 90 | 92 | 94 | % | FB/VOUT falling | 4 |
| RESET Output Level Low | | | | 0.2 | V | IRESET = 5mA | 4 |
| RESET Output Leakage Current | | | | 0.1 | µA | VRESET = 5.5V, TA = +25°C | 4 |
| VIN to GND (absolute maximum) | | -0.3 | | 70 | V | | 2 |
| EN/UVLO to GND (absolute maximum) | | -0.3 | | 70 | V | | 2 |
| LX to GND (absolute maximum) | | -0.3 | | | V | maximum is VIN + 0.3V | 2 |
| VCC, FB/VOUT, RESET to GND (absolute maximum) | | -0.3 | | 6 | V | | 2 |
| MODE to GND (absolute maximum) | | -0.3 | | | V | maximum is VCC + 0.3V | 2 |
| LX Total RMS Current | | -800 | | 800 | mA | | 2 |
| Junction Temperature | | | | 150 | °C | | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Soldering Temperature (reflow) | | | | 260 | °C | | 2 |
| Lead Temperature (soldering, 10s) | | | | 300 | °C | 10s | 2 |
| Junction-to-Ambient Thermal Resistance | θJA | | 162 | | °C/W | TDFN, JESD51-7 four-layer board | 2 |
| Junction-to-Case Thermal Resistance | θJC | | 20 | | °C/W | TDFN | 2 |
| Operating Ambient Temperature Range | TA | -40 | | 125 | °C | | 1 |
| Operating Junction Temperature Range | TJ | -40 | | 150 | °C | | 1 |
## CAD (KiCad official)
- Symbol: `MAX15062BATA+T`
- Footprint: `Package_DFN_QFN:WDFN-8-1EP_2x2mm_P0.5mm_EP0.8x1.2mm`
- 3D model: WDFN-8(2x2), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `max15062bata-t-etched.step` / `max15062bata-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `max15062bata-t.step` / `max15062bata-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices Inc Maxim Integrated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881809513304064) (23 pp, sha256 `ffeeecba16f5442d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/max15062bata-t-datasheet.pdf)