component

MAX14921ECS+T

Public Made by Adom

by adom

Analog Devices Inc Maxim Integrated Battery Management, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)max14921ecs+tfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

MAX14921ECS+T

Analog Devices Inc Maxim Integrated · Battery Management · TQFP-80(12x12)

MAX14921ECS+T from Analog Devices Inc Maxim Integrated, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input SPI clock input for the daisy-chainable SPI control interface.
2 SDI input SPI data line input.
3 SDO output SPI data line output.
4 SAMPL input Sample control input; CV_ voltages are tracked while SAMPL is logic-high and are held internally when SAMPL transitions from high to low.
5 VL power_in Logic supply input that should be bypassed to DGND with a 0.1µF capacitor placed as close as possible to the device.
6 DGND power_in Digital ground.
7 T3 input Single-ended voltage input that can be connected to a temperature sensor or other analog voltage.
8 T2 input Single-ended voltage input that can be connected to a temperature sensor or other analog voltage.
9 T1 input Single-ended voltage input that can be connected to a temperature sensor or other analog voltage.
10 AOUT output Buffered amplifier output whose voltage is relative to CV0.
11 AGND power_in Low-noise analog ground; connect CV0 to AGND and connect DGND to AGND.
12 VA power_out +5V LDO output that should be bypassed to AGND with a 1µF capacitor placed as close as possible to the device.
13 LDOIN power_in +5V LDO power supply; connect to VP to enable the LDO or to VA to disable the LDO and use an external +5V supply.
14 VP power_in Power supply connected to the highest voltage of the battery cell stack; bypass to AGND with a 0.1µF capacitor placed as close as possible to the device.
15 CV16 input Cell voltage input 16 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
16 BA16 output Cell-balancing gate driver output 16 that connects to the gate of an external n-channel FET; leave unconnected if not used.
17 CT16 passive Sampling capacitor 16 high terminal that internally connects to CV16 when SAMPL is logic-high; connect a 1µF capacitor between CT16 and CB16, or leave unconnected if not used.
18 CB16 passive Sampling capacitor 16 low terminal that internally connects to CV15 when SAMPL is logic-high; connect a 1µF capacitor between CT16 and CB16, or leave unconnected if not used.
19 CV15 input Cell voltage input 15 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
20 BA15 output Cell-balancing gate driver output 15 that connects to the gate of an external n-channel FET; leave unconnected if not used.
21 CT15 passive Sampling capacitor 15 high terminal that internally connects to CV15 when SAMPL is logic-high; connect a 1µF capacitor between CT15 and CB15, or leave unconnected if not used.
22 CB15 passive Sampling capacitor 15 low terminal that internally connects to CV14 when SAMPL is logic-high; connect a 1µF capacitor between CT15 and CB15, or leave unconnected if not used.
23 CV14 input Cell voltage input 14 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
24 BA14 output Cell-balancing gate driver output 14 that connects to the gate of an external n-channel FET; leave unconnected if not used.
25 CT14 passive Sampling capacitor 14 high terminal that internally connects to CV14 when SAMPL is logic-high; connect a 1µF capacitor between CT14 and CB14, or leave unconnected if not used.
26 CB14 passive Sampling capacitor 14 low terminal that internally connects to CV13 when SAMPL is logic-high; connect a 1µF capacitor between CT14 and CB14, or leave unconnected if not used.
27 CV13 input Cell voltage input 13 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
28 BA13 output Cell-balancing gate driver output 13 that connects to the gate of an external n-channel FET; leave unconnected if not used.
29 CT13 passive Sampling capacitor 13 high terminal that internally connects to CV13 when SAMPL is logic-high; connect a 1µF capacitor between CT13 and CB13, or leave unconnected if not used.
30 CB13 passive Sampling capacitor 13 low terminal that internally connects to CV12 when SAMPL is logic-high; connect a 1µF capacitor between CT13 and CB13, or leave unconnected if not used.
31 CV12 input Cell voltage input 12 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
32 BA12 output Cell-balancing gate driver output 12 that connects to the gate of an external n-channel FET; leave unconnected if not used.
33 CT12 passive Sampling capacitor 12 high terminal that internally connects to CV12 when SAMPL is logic-high; connect a 1µF capacitor between CT12 and CB12, or leave unconnected if not used.
34 CB12 passive Sampling capacitor 12 low terminal that internally connects to CV11 when SAMPL is logic-high; connect a 1µF capacitor between CT12 and CB12, or leave unconnected if not used.
35 CV11 input Cell voltage input 11 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
36 BA11 output Cell-balancing gate driver output 11 that connects to the gate of an external n-channel FET; leave unconnected if not used.
37 CT11 passive Sampling capacitor 11 high terminal that internally connects to CV11 when SAMPL is logic-high; connect a 1µF capacitor between CT11 and CB11, or leave unconnected if not used.
38 CB11 passive Sampling capacitor 11 low terminal that internally connects to CV10 when SAMPL is logic-high; connect a 1µF capacitor between CT11 and CB11, or leave unconnected if not used.
39 CV10 input Cell voltage input 10 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
40 BA10 output Cell-balancing gate driver output 10 that connects to the gate of an external n-channel FET; leave unconnected if not used.
41 CT10 passive Sampling capacitor 10 high terminal that internally connects to CV10 when SAMPL is logic-high; connect a 1µF capacitor between CT10 and CB10, or leave unconnected if not used.
42 CB10 passive Sampling capacitor 10 low terminal that internally connects to CV9 when SAMPL is logic-high; connect a 1µF capacitor between CT10 and CB10, or leave unconnected if not used.
43 CV9 input Cell voltage input 9 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
44 BA9 output Cell-balancing gate driver output 9 that connects to the gate of an external n-channel FET; leave unconnected if not used.
45 CT9 passive Sampling capacitor 9 high terminal that internally connects to CV9 when SAMPL is logic-high; connect a 1µF capacitor between CT9 and CB9, or leave unconnected if not used.
46 CB9 passive Sampling capacitor 9 low terminal that internally connects to CV8 when SAMPL is logic-high; connect a 1µF capacitor between CT9 and CB9, or leave unconnected if not used.
47 CV8 input Cell voltage input 8 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
48 BA8 output Cell-balancing gate driver output 8 that connects to the gate of an external n-channel FET; leave unconnected if not used.
49 CT8 passive Sampling capacitor 8 high terminal that internally connects to CV8 when SAMPL is logic-high; connect a 1µF capacitor between CT8 and CB8, or leave unconnected if not used.
50 CB8 passive Sampling capacitor 8 low terminal that internally connects to CV7 when SAMPL is logic-high; connect a 1µF capacitor between CT8 and CB8, or leave unconnected if not used.
51 CV7 input Cell voltage input 7 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
52 BA7 output Cell-balancing gate driver output 7 that connects to the gate of an external n-channel FET; leave unconnected if not used.
53 CT7 passive Sampling capacitor 7 high terminal that internally connects to CV7 when SAMPL is logic-high; connect a 1µF capacitor between CT7 and CB7, or leave unconnected if not used.
54 CB7 passive Sampling capacitor 7 low terminal that internally connects to CV6 when SAMPL is logic-high; connect a 1µF capacitor between CT7 and CB7, or leave unconnected if not used.
55 CV6 input Cell voltage input 6 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
56 BA6 output Cell-balancing gate driver output 6 that connects to the gate of an external n-channel FET; leave unconnected if not used.
57 CT6 passive Sampling capacitor 6 high terminal that internally connects to CV6 when SAMPL is logic-high; connect a 1µF capacitor between CT6 and CB6, or leave unconnected if not used.
58 CB6 passive Sampling capacitor 6 low terminal that internally connects to CV7 when SAMPL is logic-high; connect a 1µF capacitor between CT6 and CB6, or leave unconnected if not used.
59 CV5 input Cell voltage input 5 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
60 BA5 output Cell-balancing gate driver output 5 that connects to the gate of an external n-channel FET; leave unconnected if not used.
61 CT5 passive Sampling capacitor 5 high terminal that internally connects to CV5 when SAMPL is logic-high; connect a 1µF capacitor between CT5 and CB5, or leave unconnected if not used.
62 CB5 passive Sampling capacitor 5 low terminal that internally connects to CV4 when SAMPL is logic-high; connect a 1µF capacitor between CT5 and CB5, or leave unconnected if not used.
63 CV4 input Cell voltage input 4 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
64 BA4 output Cell-balancing gate driver output 4 that connects to the gate of an external n-channel FET; leave unconnected if not used.
65 CT4 passive Sampling capacitor 4 high terminal that internally connects to CV4 when SAMPL is logic-high; connect a 1µF capacitor between CT4 and CB4, or leave unconnected if not used.
66 CB4 passive Sampling capacitor 4 low terminal that internally connects to CV3 when SAMPL is logic-high; connect a 1µF capacitor between CT4 and CB4, or leave unconnected if not used.
67 CV3 input Cell voltage input 3 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
68 BA3 output Cell-balancing gate driver output 3 that connects to the gate of an external n-channel FET; leave unconnected if not used.
69 CT3 passive Sampling capacitor 3 high terminal that internally connects to CV3 when SAMPL is logic-high; connect a 1µF capacitor between CT3 and CB3, or leave unconnected if not used.
70 CB3 passive Sampling capacitor 3 low terminal that internally connects to CV2 when SAMPL is logic-high; connect a 1µF capacitor between CT3 and CB3, or leave unconnected if not used.
71 CV2 input Cell voltage input 2 connected to cell anode/cathode; connect to the highest voltage of the battery cell stack if not used.
72 BA2 output Cell-balancing gate driver output 2 that connects to the gate of an external n-channel FET; leave unconnected if not used.
73 CT2 passive Sampling capacitor 2 high terminal that internally connects to CV2 when SAMPL is logic-high; connect a 1µF capacitor between CT2 and CB2, or leave unconnected if not used.
74 CB2 passive Sampling capacitor 2 low terminal that internally connects to CV1 when SAMPL is logic-high; connect a 1µF capacitor between CT2 and CB2, or leave unconnected if not used.
75 CV1 input Cell voltage input 1 connected to cell anode/cathode.
76 BA1 output Cell-balancing gate driver output 1 that connects to the gate of an external n-channel FET; leave unconnected if not used.
77 CT1 passive Sampling capacitor connection 1 high terminal that internally connects to CV1 when SAMPL is logic-high; connect a 1µF capacitor between CT1 and CV0, or leave unconnected if not used.
78 CV0 input Cell voltage input 0 that must be connected to AGND.
79 EN input Enable input; drive low to put the device into shutdown mode and reset the SPI registers (the +5V LDO remains active), and drive high for normal operation.
80 CS input SPI chip-select input, active low.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TQFP-80(12x12)
Category Power Management (PMIC)
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VP pin voltage (absolute maximum) VP -0.3 70 V Referenced to AGND 2
VA pin voltage (absolute maximum) VA -0.3 6 V Referenced to AGND 2
VL pin voltage (absolute maximum) VL -0.3 5.5 V Referenced to AGND 2
CV0, DGND pin voltage (absolute maximum) CV0, DGND -0.3 0.3 V Referenced to AGND 2
SCLK, SDI, CS, EN pin voltage (absolute maximum) SCLK, SDI, CS, EN -0.3 6 V Referenced to AGND 2
CV1 pin voltage (absolute maximum) CV1 -0.3 6 V Referenced to AGND 2
Operating temperature range TA -40 85 °C 2
Maximum junction temperature TJ 150 °C 2
Storage temperature range TSTG -65 150 °C 2
Lead temperature (soldering) 300 °C Soldering, 10s 2
Soldering temperature (reflow) 260 °C Reflow 2
VP supply voltage VP 6 65 V 2
LDOIN supply voltage VLDOIN 6 65 V 2
LDOIN supply current, LDO off ILDOIN_OFF 75 125 µA EN = low, IA = 0A 2
LDOIN supply current, LDO on ILDOIN_ON 350 500 µA EN = high, IA = 0A 2
VA analog supply voltage VA 4.75 5 5.25 V VA supply externally, VA = VLDOIN 2
VA analog supply current, off IA_OFF 50 75 µA EN = low, VA = VLDOIN 2
VA analog supply current, on IA_ON 350 450 µA EN = high, VA = VLDOIN 2
VL supply voltage VL 1.62 5.5 V 2
VL supply current IL 2.5 5 µA All logic inputs static, held at logic-low or logic-high 2
VP supply current, on IP_ON 65 150 µA EN = high 2
LDOIN UVLO threshold UV_LDOINVT 5.25 6 V VLDOIN rising 3
LDO output voltage VA_LDO_OUT 4.75 5 5.25 V 0 < ILOAD < 10mA 3
Analog input signal range (T_) VT 0 V Reference to AGND 3
Input leakage current, T_ route to buffer amplifier IT_LEAK -1 1 µA T_ route to buffer amplifier 3
Input leakage current, T_ route to AOUT IT_LEAK -1 1 µA T_ route to AOUT 3
Capacitor discharge current ILT_ -1 1 µA Hold phase, SAMPL = low 3
Differential input signal range for guaranteed accuracy VDn 0.5 4.5 V VCVn, VCVn-1 (Note 3) 3
CV1 input voltage range VCV1 0 5 V 3
CV2-CV16 input voltage range (MAX14921) VCVm 1.5 65 V m ≥ 2, VCVm ≥ VCVm-1 (Note 3) 3
Input leakage current, sampling phase ILS_ -1 1 µA During sampling phase 3
Input leakage current, holding phase ILH_ -1 10 µA During holding phase 3
Input leakage current, calibration ILC_ -1 10 µA During calibration 3
Balancing input current ILB_ 6.5 12 mA BA_ active, VCVn - VCVn-1 = +4.5V (Note 3) 3
Sample switch on-resistance RSAMPLE 80 150 Ω VCVn > +2V, ISINK = 2mA (Note 3) 3
Sample switch on-resistance during charge injection error calibration RSWCAL 800 16000 Ω VCVn > +2V, ISINK = 2mA (Note 3), during charge injection error calibration 3
Cell undervoltage threshold UV_VCVTH 1.4 1.5 1.6 V An undervoltage sets the associated SPI Cn bit 3
AOUT output signal range VAOUT 0.3 V Reference to AGND 4
Amplifier offset voltage VOFFSET -100 100 µV VAOUT = +3.3V, after self-calibration (Note 5) 4
Temperature offset drift -1.5 1.5 µV/°C If not recalibrated 4
Output error VO_ERR -0.5 0.5 mV (Note 4) 4
Amplifier gain error VGAIN_ERR -0.2 0.2 mV ROUT = 100kΩ, VD = 2V to 4.5V (Note 6) 4
VP monitor accuracy VPMONA -0.25 0 2.5 % [SC0, SC1, SC2, SC3] = [0, 0, 1, 1] 4
Pulldown resistance (charge-balance drivers) RPDWN 10.5 14.8 21.5 kΩ 4
SDO output low voltage VOL 0.4 V ISINK = 10mA 4
SDO output leakage current IL -1 1 µA VCS = VL 4
Logic input leakage current (SDI, SCLK, EN, SAMPL) IL -1 1 µA 4
Level-shifting delay time tLS_DELAY 25 50 µs Delay from SMPLB set to 1 or SAMPL falling edge to shifting of all cell voltages to ground and available for reading 5
VP settling time tVPS 25 60 µs Measured between VP/12 (MAX14920), VP/16 (MAX14921) input selection and AOUT, settling to 2.5%, CLOAD = 100pF, SC3 = 1 5
Thermal shutdown 140 °C 5
Thermal shutdown hysteresis 15 °C 5
VP supply current, off IP_OFF 1 µA EN = low or LOPW = 1 2
VP UVLO threshold UV_VPVTH 6 V VP rising 3
UVLO hysteresis (VP) UV_VPHYST 200 mV 3
VA UVLO threshold UV_VAVTH 4.7 V VA rising 3
VL UVLO threshold UV_VLVTH 1.6 V VL rising 3
Amplifier gain A_V 1 V/V Gain = VAOUT/VD 4

CAD (KiCad official)

  • Symbol: MAX14921ECS+T
  • Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
  • 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: max14921ecs-t-etched.step / max14921ecs-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max14921ecs-t.step / max14921ecs-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (30 pp, sha256 f2fc78d7eb80734b, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF