MAX12930EASA+T from Analog Devices Inc./Maxim Integrated, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDA	power_in	Power supply for side A (1.71V to 5.5V), bypass with a 0.1µF ceramic capacitor to GNDA.
2	IN1	input	Logic input for channel 1, referenced to GNDA.
3	IN2	input	Logic input for channel 2, referenced to GNDA.
4	GNDA	power_in	Ground reference for side A.
5	GNDB	power_in	Ground reference for side B.
6	OUT2	output	Push-pull logic output of channel 2, referenced to GNDB.
7	OUT1	output	Push-pull logic output of channel 1, referenced to GNDB.
8	VDDB	power_in	Power supply for side B (1.71V to 5.5V), bypass with a 0.1µF ceramic capacitor to GNDB.

Key specifications

Parameter	Value
Manufacturer	Analog Devices Inc./Maxim Integrated
Package	SOIC-8
Category	Signal Isolation Devices
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage A	VDDA	1.71		5.5	V	Relative to GNDA	3
Supply Voltage B	VDDB	1.71		5.5	V	Relative to GNDB	3
Undervoltage-Lockout Threshold	VUVLO_	1.5	1.6	1.66	V	VDD_ rising	3
Undervoltage-Lockout Threshold Hysteresis	VUVLO_HYST		45		mV		3
Supply Current Side A, 1MHz	IDDA		0.31	0.54	mA	1MHz square wave, CL = 0pF, VDDA = 3.3V	3
Supply Current Side A, 12.5MHz	IDDA		0.8	1.2	mA	12.5MHz square wave, CL = 0pF, VDDA = 3.3V	3
Supply Current Side A, 50MHz	IDDA		2.09	2.91	mA	50MHz square wave, CL = 0pF, VDDA = 3.3V	3
Supply Current Side B, 1MHz	IDDB		0.47	0.79	mA	1MHz square wave, CL = 0pF, VDDB = 3.3V	3
Supply Current Side B, 12.5MHz	IDDB		1.02	1.4	mA	12.5MHz square wave, CL = 0pF, VDDB = 3.3V	3
Supply Current Side B, 50MHz	IDDB		2.81	3.39	mA	50MHz square wave, CL = 0pF, VDDB = 3.3V	3
Input High Voltage (x VDD_)	VIH	0.7			x VDD_	2.25V ≤ VDD_ ≤ 5.5V	4
Input High Voltage (x VDD_)	VIH	0.75			x VDD_	1.71V ≤ VDD_ < 2.25V	4
Input Low Voltage	VIL			0.8	V	2.25V ≤ VDD_ ≤ 5.5V	4
Input Low Voltage	VIL			0.7	V	1.71V ≤ VDD_ < 2.25V	4
Input Hysteresis	VHYS		410		mV	MAX1293_B/E	4
Input Pulldown Current	IPD	1.5	5	10	µA	IN_, MAX1293_E/F	4
Input Capacitance	CIN		2		pF	IN_, fSW = 1MHz	4
Output Voltage Low	VOL			0.4	V	IOUT = 4mA sink	5
Common-Mode Transient Immunity	CMTI		50		kV/µs	IN_ = GND_ or VDD_	5
Maximum Data Rate	DRMAX		25		Mbps		5
Minimum Pulse Width	PWMIN			40	ns		5
Glitch Rejection		10	17	29	ns		5
Propagation Delay tPLH	tPLH	17.4	23.9	32.5	ns	4.5V ≤ VDD_ ≤ 5.5V	5
Propagation Delay tPLH	tPLH	17.6	24.4	33.7	ns	3.0V ≤ VDD_ ≤ 3.6V	5
Propagation Delay tPLH	tPLH	18.3	25.8	36.7	ns	2.25V ≤ VDD_ ≤ 2.75V	5
Propagation Delay tPLH	tPLH	20.7	29.6	43.5	ns	1.71V ≤ VDD_ ≤ 1.89V	5
Propagation Delay tPHL	tPHL	16.9	23.4	33.6	ns	4.5V ≤ VDD_ ≤ 5.5V	5
Propagation Delay tPHL	tPHL	17.2	24.2	35.1	ns	3.0V ≤ VDD_ ≤ 3.6V	5
Propagation Delay tPHL	tPHL	17.8	25.4	38.2	ns	2.25V ≤ VDD_ ≤ 2.75V	5
Propagation Delay tPHL	tPHL	19.8	29.3	45.8	ns	1.71V ≤ VDD_ ≤ 1.89V	5
Pulse Width Distortion	PWD		0.4	4	ns		5
Channel-to-Channel Skew (Same Direction)	tSCSLH			2	ns	MAX12930 only	5
Peak Eye Diagram Jitter	TJIT(PK)		250		ps	25Mbps	6
VDDA to GNDA	VDDA	-0.3		6	V		2
VDDB to GNDB	VDDB	-0.3		6	V		2
IN_ to respective GND	IN_	-0.3		6	V	Side A to GNDA, Side B to GNDB	2
Operating Temperature Range	TA	-40		125	°C		2
Maximum Junction Temperature	TJ			150	°C		2
Storage Temperature Range	TSTG	-60		150	°C		2
Soldering Temperature (reflow)				260	°C		2
Junction to Ambient Thermal Resistance	θJA		172.8		°C/W	8 Narrow SOIC, four-layer board	2
Junction to Case Thermal Resistance	θJC		67.6		°C/W	8 Narrow SOIC, four-layer board	2
ESD Human Body Model		-3		3	kV	all pins	8
Maximum Withstand Isolation Voltage	VISO			3000	VRMS	fSW = 60Hz, duration = 60s	10
Barrier Capacitance Side A to Side B	CIO		2		pF	fSW = 1MHz	10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pet		The MAX12930-MAX12931 narrow-body SOIC are certified to DIN VDE V 0884-11: 2017-01 Basic Insulation, Maximum Transient Isolation Voltage 4200VPK, Maximum Repetitive Peak Isolation Voltage 630VPK.	9

CAD (KiCad official)

Symbol: MAX12930EASA+T
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: max12930easa-t-etched.step / max12930easa-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max12930easa-t.step / max12930easa-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices Inc./Maxim Integrated datasheet (24 pp, sha256 1082a23cefedacbf, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MAX12930EASA+T

Verified MAX12930EASA+T

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3D Model

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Schematic Symbol

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Datasheet

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