component

MA12070P

Public Made by Adom

by adom

Infineon Technologies Audio Power OpAmps, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifiersma12070pfactory-2.0.0extractor-text

Verified MA12070P

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MA12070P · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 88-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-csheqmrn/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ma12070p.kicad_sym✓ ma12070p.kicad_mod✓ ma12070p.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ma12070p / README.md
History Download
Ray Publish 0.1.0 190f5b7 18h ago

MA12070P

Infineon Technologies · Audio Power OpAmps · QFN-64-EP(9x9)

MA12070P from Infineon Technologies, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVSS power_in Power ground for internal power amplifiers.
2 PVSS power_in Power ground for internal power amplifiers.
3 CF0AN power_in Connect to external flying capacitor negative terminal for amplifier channel 0A.
4 OUT0A output Audio power output 0A.
5 OUT0A output Audio power output 0A.
6 CF0AP power_in Connect to external flying capacitor positive terminal for amplifier channel 0A.
7 PVDD power_in Power supply for internal power amplifiers.
8 PVDD power_in Power supply for internal power amplifiers.
9 CF0BP power_in Connect to external flying capacitor positive terminal for amplifier channel 0B.
10 OUT0B output Audio power output 0B.
11 OUT0B output Audio power output 0B.
12 CF0BN power_in Connect to external flying capacitor negative terminal for amplifier channel 0B.
13 PVSS power_in Power ground for internal power amplifiers.
14 PVSS power_in Power ground for internal power amplifiers.
15 /CLIP output Audio clipping indicator (open drain output), pulled low when clipping occurs.
16 /ERROR output Error indicator (open drain output), pulled low when an error occurs.
17 AVDD power_in Power supply for internal analog circuitry.
18 CMSE output Decoupling pin for internally generated common-mode voltage in SE configuration; should be externally decoupled to AVSS and can be left floating for 2 x BTL and PBTL configurations.
19 AVSS power_in Ground for internal analog circuitry.
20 CREF output Decoupling pin for internally generated analog reference voltage; should be externally decoupled to AVSS.
21 SCK input I2S digital audio serial clock; must be synchronized to CLK.
22 WS input I2S digital audio word select; must be synchronized to CLK.
23 SD0 input I2S digital audio serial data pair 0.
24 SD1 input I2S digital audio serial data pair 1.
25 AVSS power_in Ground for internal analog circuitry.
26 DVSS power_in Ground for internal digital circuitry.
27 SCL bidirectional I2C bus serial clock.
28 AD0 input I2C device address select 0.
29 AD1 input I2C device address select 1.
30 SDA bidirectional I2C bus serial data.
31 CLKM/S input Reserved; must be pulled low.
32 CLK input Clock input; must be present before enabling the amplifier.
33 /ENABLE input When pulled high, the device is reset and kept in an inactive state with minimum power consumption.
34 /MUTE input Mutes audio output when pulled low.
35 PVSS power_in Power ground for internal power amplifiers.
36 PVSS power_in Power ground for internal power amplifiers.
37 CF1BN power_in Connect to external flying capacitor negative terminal for amplifier channel 1B.
38 OUT1B output Audio power output 1B.
39 OUT1B output Audio power output 1B.
40 CF1BP power_in Connect to external flying capacitor positive terminal for amplifier channel 1B.
41 PVDD power_in Power supply for power amplifiers.
42 PVDD power_in Power supply for power amplifiers.
43 CF1AP power_in Connect to external flying capacitor positive terminal for amplifier channel 1A.
44 OUT1A output Audio power output 1A.
45 OUT1A output Audio power output 1A.
46 CF1AN power_in Connect to external flying capacitor negative terminal for amplifier channel 1A.
47 PVSS power_in Power ground for internal power amplifiers.
48 PVSS power_in Power ground for internal power amplifiers.
49 NC unconnected Internally connected to DVDD.
50 MSEL1 input SE/BTL/PBTL configuration select 1.
51 MSEL0 input SE/BTL/PBTL configuration select 0.
52 CGD1N power_in Connect to external decoupling capacitor negative terminal for internal gate driver power supply 1.
53 CGD1P power_in Connect to external decoupling capacitor positive terminal for internal gate driver power supply 1.
54 VGDC power_in Internally generated virtual ground voltage for digital core; should be decoupled to DVDD.
55 DVDD power_in Power supply for internal digital circuitry and charge pumps.
56 CDC power_in Connect to external decoupling capacitor for digital core internal power supply.
57 CFDCP power_in Connect to external flying capacitor positive terminal for internal digital core power supply.
58 CFDCN power_in Connect to external flying capacitor negative terminal for internal digital core power supply.
59 DVSS power_in Power ground for internal digital circuitry.
60 CGD0P power_in Connect to external decoupling capacitor positive terminal for internal gate driver power supply 0.
61 CGD0N power_in Connect to external decoupling capacitor negative terminal for internal gate driver power supply 0.
62 CFGDP power_in Connect to external flying capacitor positive terminal for internal gate driver power supplies.
63 CFGDN power_in Connect to external flying capacitor negative terminal for internal gate driver power supplies.
64 NC unconnected Internally connected to DVDD.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package QFN-64-EP(9x9)
Category Amplifiers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power stage power supply PVDD 5 26 V Power Stage Power Supply 8
Digital power supply DVDD 4.75 5 5.25 V Digital Power Supply 8
Analog power supply AVDD 4.75 5 5.25 V Analog Power Supply 8
High level for logic, clock, interface VIH 2 V High Level for Logic, Clock, Interface 8
Low level for logic, clock, interface VIL 0.8 V Low Level for Logic, Clock, Interface 8
DC offset level for analog inputs VIN_dc 1.2 2.5 3.8 V DC Offset Level for Analog Inputs 8
Audio signal level for analog inputs VIN_ac 1.8 Vpp Audio Signal Level for Analog Inputs 8
Minimum load in bridge-tied load mode RL (BTL) 3.2 4 Ω Minimum Load in Bridge-Tied Load Mode 8
Minimum load in parallel bridge-tied load mode RL (PBTL) 1.6 2 Ω Minimum Load in Parallel Bridge-Tied Load Mode 8
Minimum load in single ended mode RL (SE) 2.4 3 Ω Minimum Load in Single Ended Mode 8
Minimum required equivalent load inductance per output pin LLeq 0.5 µH Minimum required equivalent load inductance per output pin for short circuit protection 8
Ambient temperature range TA 0 25 85 °C Ambient temperature range 8
Power stage supply voltage PVDD -0.5 27.5 V Power stage supply voltage 7
System supply voltage DVDD, AVDD -0.5 6 V System supply voltage DVDD, AVDD 7
Analog input voltage IN0A, IN0B, IN1A, IN1B -0.5 6 V Analog inputs 7
Logic input voltage /ENABLE, /MUTE, /ERROR, /CLIP, MSEL0, MSEL1 -0.5 6 V Logic inputs and outputs 7
Clock voltage CLKIO, CLKM/S -0.5 6 V Clock pins 7
Interface voltage SCL, SDA, AD0, AD1 -0.5 6 V Interface pins 7
Output current, logic and interface 25 mA Logic and interface outputs 7
Ambient temperature range TA -40 85 °C Ambient temperature range 7
Junction temperature range TJ -40 150 °C Junction temperature range 7
Storage temperature range -65 150 °C Storage temperature range 7
Lead soldering temperature 300 °C 10 s 7
Electrostatic discharge, human body model HBM -2000 2000 V Human body model 7
Electrostatic discharge, charged device model CDM -1000 1000 V Charged device model 7
Shutdown/full operation timing TENABLE 1 ms NENABLE = 1 → 0 9
Mute/unmute timing TMUTE 0.3 ms NMUTE = 1 → 0 and 0 → 1 9
Output offset voltage VOS -200 200 mV Output Offset Voltage 9
Power supply rejection ratio PSRR 70 dB ± 100mVpp ripple voltage 9
Resistance, switch on Ron 0.1 0.15 0.2 Ω Resistance, switch on 9
Power MOSFET switching frequency, Power Mode A fSW 618 672 726 kHz Power Mode A 9
Power MOSFET switching frequency, Power Mode B & C fSW 316 336 356 kHz Power Mode B & C 9
Power MOSFET switching frequency, Power Mode D fSW 158 168 178 kHz Power Mode D 9
Clock output frequency fCLK_IO 2.7151 2.8224 2.9296 MHz Clock output frequency 9
Maximum output current IOUT 8 A Maximum Output Current 9
Output power per channel (peak), BTL POUT (BTL) 45 W THD+N = 10%, RL = 8Ω, f = 1kHz 9
Output power per channel (peak), BTL POUT (BTL) 80 W THD+N = 10%, RL = 4Ω, f = 1kHz 9
Output power per channel (peak), BTL POUT (BTL) 35 W THD+N = 1%, RL = 8Ω, f = 1kHz 9
Output power per channel (peak), BTL POUT (BTL) 60 W THD+N = 1%, RL = 4Ω, f = 1kHz 9
Output power per channel (continuous) 30 W RL = 8Ω, f = 1kHz, PVDD = +22V 9
Output power (peak), PBTL POUT (PBTL) 160 W THD+N = 10%, RL = 2Ω, f = 1kHz 9
Output power (peak), PBTL POUT (PBTL) 120 W THD+N = 1%, RL = 2Ω, f = 1kHz 9
Output power per channel (peak), SE POUT (SE) 20 W THD+N = 10%, RL = 4Ω, f = 1kHz 9
Output power per channel (peak), SE POUT (SE) 25 W THD+N = 10%, RL = 3Ω, f = 1kHz 9
Output power per channel (peak), SE POUT (SE) 15 W THD+N = 1%, RL = 4Ω, f = 1kHz 9
Current consumption, PVDD shutdown Ishutdown 10 35 180 µA Current Consumption, PVDD Shutdown 11
Current consumption, PVDD idle, mute Iidle,mute 4 6 12 mA Current Consumption, PVDD Idle, mute 11
Current consumption, PVDD idle, unmute Iidle,unmute 4 9 18 mA Idle, unmute, inputs grounded 11
Current consumption, AVDD+DVDD idle, unmute IDVDD+AVDD 30 35 42 mA Idle, unmute, inputs grounded 11
Total harmonic distortion + noise THD+N 0.013 % 1kHz, POUT = 1W, RL = 4Ω 11
Total harmonic distortion + noise THD+N 0.014 % 1kHz, POUT = 20W, RL = 4Ω 11
Dynamic range DNR 100 dB 20-20kHz, A-weighted 11
Output integrated noise level Vnoise 105 150 190 µVrms 20-20kHz, A-weighted 11

CAD (KiCad official)

  • Symbol: MA12070P
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ma12070p-etched.step / ma12070p-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ma12070p.step / ma12070p.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (88 pp, sha256 b85e9c5028610c61, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF