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m95m04-drmn6tp: factory component page (tier=lcsc)

Ray ·f5eb454d40 ·27d ago ·parent eb2c896
1 file changed +130−8
page.json+130−8
@@ -1,13 +1,140 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "m95m04-drmn6tp",+  "title": "M95M04-DRMN6TP",+  "brief": "STMicroelectronics EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "STMicroelectronics EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "memory",     "m95m04-drmn6tp"   ],+  "component": {+    "mpn": "M95M04-DRMN6TP",+    "manufacturer": "STMicroelectronics",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Memory",+    "subcategory": "EEPROM",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_STMicroelectronics-M95M04-DRMN6TP_C1852765.pdf",+    "parts": {+      "symbol": "m95m04-drmn6tp.kicad_sym",+      "footprint": "m95m04-drmn6tp.kicad_mod",+      "model_3d": "m95m04-drmn6tp.glb",+      "model_3d_step": "m95m04-drmn6tp.step",+      "lbr": "m95m04-drmn6tp.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "S#",+        "type": "input",+        "description": "Chip select (active low). Driving S# low selects the device and places it in active power mode; driving it high deselects the device and puts Q into high impedance. A falling edge on S# is required after power-up before the first instruction."+      },+      {+        "number": "2",+        "name": "Q",+        "type": "output",+        "description": "Serial data output (MISO). Data is shifted out on the falling edge of the serial clock C, MSB first. High impedance when the device is deselected or in hold condition."+      },+      {+        "number": "3",+        "name": "W#",+        "type": "input",+        "description": "Write protect (active low). When low with SRWD=1, freezes the block-protect bits (BP1, BP0) in the status register, protecting the write-protected block of the memory array. Must be driven high or low, stable during writes."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground reference for the Vcc supply and for all input and output signals."+      },+      {+        "number": "5",+        "name": "D",+        "type": "input",+        "description": "Serial data input (MOSI). Receives instructions, addresses, and write data. Latched on the rising edge of serial clock C, MSB first."+      },+      {+        "number": "6",+        "name": "C",+        "type": "input",+        "description": "Serial clock input. Latches D on the rising edge and shifts Q on the falling edge. Supports SPI mode 0 (CPOL=0, CPHA=0) or mode 3 (CPOL=1, CPHA=1). Max 10 MHz at Vcc >= 2.5 V, 5 MHz at Vcc >= 1.8 V."+      },+      {+        "number": "7",+        "name": "HOLD#",+        "type": "input",+        "description": "Hold (active low). When driven low with the device selected (S# low), pauses serial communications without deselecting the device; Q goes to high impedance and D and C become don't-care. Must be driven high in normal operation."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply voltage, 1.8 V to 5.5 V single supply. Must remain stable within the valid range during all operations and internal write cycles. Decouple to Vss with 10-100 nF close to the pin."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_STMicroelectronics-M95M04-DRMN6TP_C1852765.pdf",+        "pages": 44,+        "sha256": "c3ca0f47a94235f0",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "STMicroelectronics",+      "Package": "SOIC-8",+      "Category": "Memory",+      "Pins": "8"+    }+  },+  "variants": [+    {+      "mpn": "M95M04-DRMN6TP",+      "kind": "packaging"+    },+    {+      "mpn": "M95M04-DRMN6TPDRDW",+      "kind": "packaging"+    },+    {+      "mpn": "M95M04-DRMN6TPDRCS",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "m95m04-drmn6tp"+  ],+  "discovery_pitch": "M95M04-DRMN6TP (STMicroelectronics) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +152,5 @@     "docs/m95m04-drmn6tp-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file