component
M95M04-DRMN6TP
Public Made by Adomby adom
STMicroelectronics EEPROM, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownM95M04-DRMN6TP
STMicroelectronics · EEPROM · SOIC-8
M95M04-DRMN6TP from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S# | input | Chip select (active low). Driving S# low selects the device and places it in active power mode; driving it high deselects the device and puts Q into high impedance. A falling edge on S# is required after power-up before the first instruction. |
| 2 | Q | output | Serial data output (MISO). Data is shifted out on the falling edge of the serial clock C, MSB first. High impedance when the device is deselected or in hold condition. |
| 3 | W# | input | Write protect (active low). When low with SRWD=1, freezes the block-protect bits (BP1, BP0) in the status register, protecting the write-protected block of the memory array. Must be driven high or low, stable during writes. |
| 4 | VSS | power_in | Ground reference for the Vcc supply and for all input and output signals. |
| 5 | D | input | Serial data input (MOSI). Receives instructions, addresses, and write data. Latched on the rising edge of serial clock C, MSB first. |
| 6 | C | input | Serial clock input. Latches D on the rising edge and shifts Q on the falling edge. Supports SPI mode 0 (CPOL=0, CPHA=0) or mode 3 (CPOL=1, CPHA=1). Max 10 MHz at Vcc >= 2.5 V, 5 MHz at Vcc >= 1.8 V. |
| 7 | HOLD# | input | Hold (active low). When driven low with the device selected (S# low), pauses serial communications without deselecting the device; Q goes to high impedance and D and C become don't-care. Must be driven high in normal operation. |
| 8 | VCC | power_in | Supply voltage, 1.8 V to 5.5 V single supply. Must remain stable within the valid range during all operations and internal write cycles. Decouple to Vss with 10-100 nF close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
M95M04-DRMN6TPM95M04-DRMN6TPDRDWM95M04-DRMN6TPDRCS
CAD (KiCad official)
- Symbol:
M95M04-DRMN6TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
m95m04-drmn6tp-etched.step/m95m04-drmn6tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);m95m04-drmn6tp.step/m95m04-drmn6tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (44 pp, sha256
c3ca0f47a94235f0, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).