component
M95640-DRDW3TP
Public Made by Adomby adom
STMicroelectronics EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownM95640-DRDW3TP
STMicroelectronics · EEPROM · TSSOP-8
M95640-DRDW3TP from STMicroelectronics, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | input | Chip Select: driving S low selects the device and driving it high deselects it and puts Q in high impedance; after power-up the device is not selected until a falling edge is detected on S. |
| 2 | Q | tri_state | Serial data output: data is shifted out on the falling edge of C, MSB first, and Q is high impedance at all other times; Q voltage is limited to -0.50 V to VCC+0.6 V and DC output current to 5 mA (IOL and IOH). |
| 3 | W | input | Write Protect: used together with the SRWD bit to write-protect the Status Register, and must be driven high or low as appropriate; if SRWD is 1 and W is low, the Status Register cannot be written. |
| 4 | VSS | power_in | Ground: the reference for all signals, including the VCC supply voltage. |
| 5 | D | input | Serial data input: receives instructions, addresses and data to be written, latched on the rising edge of C, MSB first; input voltage range is -0.50 V to 6.5 V. |
| 6 | C | input | Serial clock: synchronizes the serial interface, with D latched on its rising edge and Q changing after its falling edge; maximum clock frequency is 20 MHz for VCC of 4.5 V or higher. |
| 7 | HOLD | input | Hold: pauses serial communication without deselecting the device; Hold mode starts when HOLD is driven low while C is low and ends when HOLD is driven high and C is or becomes low. |
| 8 | VCC | power_in | Supply voltage: for voltage range R the operating range is 1.7 V to 5.5 V, and a decoupling capacitor of about 10 nF to 100 nF should be placed close to the VCC/VSS pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-8 |
| Category | Memory |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
M95640-DRDW3TP - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
m95640-drdw3tp-etched.step/m95640-drdw3tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);m95640-drdw3tp.step/m95640-drdw3tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (44 pp, sha256
61948cd2b79f9222, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).