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M95512-DRMN3TP

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STMicroelectronics EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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M95512-DRMN3TP

STMicroelectronics · EEPROM · SOIC-8

M95512-DRMN3TP from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S input Chip Select, active low: driving it low selects the device and starts communication, driving it high deselects the device and puts Q in high impedance.
2 Q tri_state Serial Data output, which shifts data out on the falling edge of Serial Clock (C), MSB first, and is high impedance in all other cases.
3 W input Write Protect, used to write-protect the Status Register.
4 VSS power_in Ground, the reference for all signals including the VCC supply voltage.
5 D input Serial Data input, which receives instructions, addresses and data to be written, latched on the rising edge of Serial Clock (C), MSB first.
6 C input Serial Clock, which synchronizes the serial interface: inputs are latched on its rising edge and Q changes after its falling edge.
7 HOLD input Hold, active low: pauses serial communication with the device without deselecting it or resetting the clocking sequence.
8 VCC power_in Supply voltage, 1.7 V to 5.5 V for voltage range R (this MPN) with a 10 nF to 100 nF decoupling capacitor recommended close to the VCC/VSS pins.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -65 150 °C 29
Ambient operating temperature (absolute max) TAMR -40 150 °C 29
Input voltage VI -0.5 6.5 V 29
DC output current (Q = 0) IOL 5 mA 29
DC output current (Q = 1) IOH 5 mA 29
Supply voltage (absolute max) VCC -0.5 6.5 V 29
Electrostatic pulse (Human Body Model) VESD 4000 V 29
Supply voltage VCC 1.7 5.5 V 30
Ambient operating temperature TA -40 125 °C 30
Operating clock frequency fC 10 MHz VCC ≥ 2.5 V, capacitive load on Q pin ≤100pF 30
Operating clock frequency fC 5 MHz VCC ≥ 1.7 V, capacitive load on Q pin ≤100pF 30
Operating clock frequency (high-speed) fC 16 MHz VCC ≥ 4.5 V, capacitive load on Q pin ≤ 60 pF 30
Write cycle endurance Ncycle 4e+06 Write cycle TA ≤ 25 °C, 1.7 V < VCC < 5.5 V 30
Write cycle endurance Ncycle 1.2e+06 Write cycle TA = 85 °C, 1.7 V < VCC < 5.5 V 30
Write cycle endurance Ncycle 600000 Write cycle TA = 125 °C, 1.7 V < VCC < 5.5 V 30
Output capacitance (Q) COUT 8 pF VOUT = 0 V 32
Input capacitance CIN 6 pF VIN = 0 V 32
Input leakage current ILI 2 µA VIN = VSS or VCC 32
Output leakage current ILO 3 µA S = VCC, VOUT = VSS or VCC 32
Supply current (Read) ICC 2 mA VCC = 1.7 V, C = 0.1 VCC/0.9 VCC, Q = open, fC = 5 MHz 32
Supply current (Read) ICC 5 mA VCC = 5.5 V, fC = 16 MHz, C = 0.1 VCC/0.9 VCC, Q = open 32
Supply current (Write) ICC0 2 mA 1.7 V ≤ VCC < 5.5 V during tW, S = VCC 32
Supply current (Standby mode) ICC1 1 µA t° = 85 °C, VCC = 1.7 V, S = VCC, VIN = VSS or VCC 32
Supply current (Standby mode) ICC1 2 µA t° = 85 °C, VCC = 2.5 V, S = VCC, VIN = VSS or VCC 32
Supply current (Standby mode) ICC1 3 µA t° = 85 °C, VCC = 5.5 V, S = VCC, VIN = VSS or VCC 32
Supply current (Standby mode) ICC1 15 µA t° = 125 °C, VCC = 1.7 V, S = VCC, VIN = VSS or VCC 32
Supply current (Standby mode) ICC1 20 µA t° = 125 °C, VCC = 5.5 V, S = VCC, VIN = VSS or VCC 32
Input low voltage VIL -0.45 V 1.7 V ≤ VCC < 2.5 V 32
Output low voltage VOL 0.3 V VCC = 1.7 V, IOL = 1 mA 32
Output low voltage VOL 0.4 V VCC ≥ 2.5 V, IOL = 2 mA 32
Internal reset threshold voltage VRES 0.5 1.5 V 32
Clock frequency fC 5 MHz Test conditions specified in Table 11 33
S active setup time tSLCH 60 ns Test conditions specified in Table 11 33
S not active setup time tSHCH 60 ns Test conditions specified in Table 11 33
S deselect time tSHSL 90 ns Test conditions specified in Table 11 33
S active hold time tCHSH 60 ns Test conditions specified in Table 11 33
S not active hold time tCHSL 60 ns Test conditions specified in Table 11 33
Clock high time tCH 80 ns Test conditions specified in Table 11 33
Clock low time tCL 80 ns Test conditions specified in Table 11 33
Clock rise time tCLCH 2 µs Test conditions specified in Table 11 33
Clock fall time tCHCL 2 µs Test conditions specified in Table 11 33
Data in setup time tDVCH 20 ns Test conditions specified in Table 11 33
Data in hold time tCHDX 20 ns Test conditions specified in Table 11 33
Clock low hold time after HOLD not active tHHCH 60 ns Test conditions specified in Table 11 33
Clock low hold time after HOLD active tHLCH 60 ns Test conditions specified in Table 11 33
Clock low set-up time before HOLD active tCLHL 0 ns Test conditions specified in Table 11 33
Clock low set-up time before HOLD not active tCLHH 0 ns Test conditions specified in Table 11 33
Output disable time tSHQZ 80 ns Test conditions specified in Table 11 33
Clock low to output valid tCLQV 80 ns Test conditions specified in Table 11 33
Output hold time tCLQX 0 ns Test conditions specified in Table 11 33
Output rise time tQLQH 20 ns Test conditions specified in Table 11 33
Output fall time tQHQL 20 ns Test conditions specified in Table 11 33
HOLD high to output valid tHHQV 80 ns Test conditions specified in Table 11 33
HOLD low to output high-Z tHLQZ 80 ns Test conditions specified in Table 11 33
Write time tW 4 ms 33

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin TLEAD Lead temperature during soldering See note (1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK® 29

CAD (KiCad official)

  • Symbol: M95512-DRMN3TP
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: m95512-drmn3tp-etched.step / m95512-drmn3tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m95512-drmn3tp.step / m95512-drmn3tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (44 pp, sha256 e769a10125daa0d1, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF