M95040-DFMN6TP from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S	input	Active-low Chip Select: high deselects the device and puts Q in high impedance (standby unless a write is in progress), low selects it; a falling edge is required after power-up before any instruction.
2	Q	output	Serial Data Output: shifts data out on the falling edge of C and is high impedance when S is high or during the Hold condition.
3	W	input	Active-low Write Protect: when held low, writes to the memory are disabled while other operations stay enabled; it must be driven high or low and never left floating.
4	VSS	power_in	Ground, the reference for the VCC supply voltage.
5	D	input	Serial Data Input: receives instructions, addresses and data to be written, latched on the rising edge of C.
6	C	input	Serial Clock: provides the timing of the serial interface; inputs on D are latched on its rising edge and Q changes after its falling edge, with a maximum frequency of 20 MHz.
7	HOLD	input	Active-low Hold: pauses serial communication without deselecting the device; during Hold, Q is high impedance and D and C are don't care, and the device must be selected (S low) to enter Hold.
8	VCC	power_in	Supply voltage, 1.7 V to 5.5 V for M95040-DF, which must be stable and valid during instructions and write cycles; decoupling of 10 nF to 100 nF close to VCC/VSS is recommended.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
Supply voltage	VCC	1.7	5.5	V	M95040-DF, device grade 6	31
Ambient operating temperature	TA	-40	85	°C	device grade 6	31
Ambient operating temperature (abs max)	TAMR	-40	130	°C		30
Storage temperature	TSTG	-65	150	°C		30
Output voltage	VO	-0.5		V	max is VCC+0.6	30
Input voltage	VI	-0.5		V	max is VCC+1.0	30
DC output current (Q = 0)	IOL		5	mA		30
DC output current (Q = 1)	IIH		5	mA		30
Supply voltage (abs max)	VCC	-0.5	6.5	V		30
Electrostatic pulse (HBM)	VESD		4000	V	Human Body Model	30
Input leakage current	ILI	-2	2	µA	VIN = VSS or VCC	34
Output leakage current	ILO	-2	2	µA	S = VCC, voltage applied on Q = VSS or VCC	34
Supply current (Read)	ICC		2	mA	VCC = 1.8 V or 1.7 V, fC = 5 MHz, C = 0.1 VCC/0.9 VCC, Q = open	34
Supply current (Write)	ICC0		5	mA	VCC = 1.8 V or 1.7 V, during tW, S = VCC	34
Supply current (Standby)	ICC1		1	µA	VCC = 1.8 V or 1.7 V, S = VCC, VIN = VSS or VCC	34
Input low voltage (lower limit)	VIL	-0.45		V	VCC < 2.5 V	34
Input low voltage (upper limit, multiple of VCC)	VIL		0.25	VCC	VCC < 2.5 V	34
Input high voltage (lower limit, multiple of VCC)	VIH	0.75		VCC	VCC < 2.5 V	34
Output low voltage	VOL		0.3	V	IOL = 0.15 mA, VCC = 1.8 V or 1.7 V	34
Output high voltage (multiple of VCC)	VOH	0.8		VCC	IOH = -0.1 mA, VCC = 1.8 V or 1.7 V	34
Internal reset threshold voltage	VRES	1	1.65	V		34
Output capacitance (Q)	COUT		8	pF	VOUT = 0 V, TA=25 °C, 5 MHz, sampled	32
Input capacitance (D)	CIN		8	pF	VIN = 0 V, TA=25 °C, 5 MHz, sampled	32
Input capacitance (other pins)	CIN		6	pF	VIN = 0 V, TA=25 °C, 5 MHz, sampled	32
Data retention		200		Year	TA = 55 °C	32
Clock frequency	fC		5	MHz	Table 19, D.C. to 5	36
S active setup time	tSLCH	60		ns		36
S not active setup time	tSHCH	60		ns		36
S deselect time	tSHSL	90		ns		36
S active hold time	tCHSH	60		ns		36
S not active hold time	tCHSL	60		ns		36
Clock high time	tCH	80		ns		36
Clock low time	tCL	80		ns		36
Clock rise time	tCLCH		2	µs		36
Clock fall time	tCHCL		2	µs		36
Data in setup time	tDVCH	20		ns		36
Data in hold time	tCHDX	20		ns		36
Clock low hold time after HOLD not active	tHHCH	60		ns		36
Clock low hold time after HOLD active	tHLCH	60		ns		36
Clock low set-up time before HOLD active	tCLHL	0		ns		36
Clock low set-up time before HOLD not active	tCLHH	0		ns		36
Output disable time	tSHQZ		80	ns		36
Clock low to output valid	tCLQV		80	ns		36
Output hold time	tCLQX	0		ns		36
Output rise time	tQLQH		80	ns		36
Output fall time	tQHQL		80	ns		36
HOLD high to output valid	tHHQV		80	ns		36
HOLD low to output high-Z	tHLQZ		80	ns		36
Write time	tW		5	ms		36

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	TLEAD Lead temperature during soldering see note (1) 1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK®	30

CAD (KiCad official)

Symbol: M95040-DFMN6TP
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)
3D model files: m95040-dfmn6tp-etched.step / m95040-dfmn6tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m95040-dfmn6tp.step / m95040-dfmn6tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (46 pp, sha256 1b7ee07d5879b564, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

M95040-DFMN6TP

Verified M95040-DFMN6TP

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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