M74HCT4094ADTR2G

{
  "slug": "m74hct4094adtr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "m74hct4094adtr2g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "m74hct4094adtr2g.kicad_sym",
    "m74hct4094adtr2g.kicad_mod",
    "m74hct4094adtr2g.glb",
    "m74hct4094adtr2g.step",
    "m74hct4094adtr2g.lbr",
    "docs/hero.png",
    "docs/m74hct4094adtr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "m74hct4094adtr2g-hero.glb",
    "m74hct4094adtr2g-hero.overlay.json",
    "m74hct4094adtr2g-etched.glb"
  ],
  "component": {
    "mpn": "M74HCT4094ADTR2G",
    "manufacturer": "onsemi",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929129345929216",
    "parts": {
      "symbol": "m74hct4094adtr2g.kicad_sym",
      "footprint": "m74hct4094adtr2g.kicad_mod",
      "model_3d": "m74hct4094adtr2g-hero.glb",
      "model_3d_plain": "m74hct4094adtr2g-etched.glb",
      "model_3d_step": "m74hct4094adtr2g-etched.step",
      "model_3d_step_plain": "m74hct4094adtr2g.step",
      "lbr": "m74hct4094adtr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C903823"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T22:12:01Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "STR",
        "type": "input",
        "description": "Strobe input: when high, the data in the 8-bit shift register is transferred to the storage register."
      },
      {
        "number": "2",
        "name": "D",
        "type": "input",
        "description": "Serial data input to the shift register, with a minimum set-up time of 10 ns and minimum hold time of 3 ns to CP at VCC = 4.5 V."
      },
      {
        "number": "3",
        "name": "CP",
        "type": "input",
        "description": "Clock input: data is shifted on positive (LOW-to-HIGH) clock transitions, with a minimum clock pulse width of 16 ns at VCC = 4.5 V."
      },
      {
        "number": "4",
        "name": "QP0",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 0, high impedance when OE is low."
      },
      {
        "number": "5",
        "name": "QP1",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 1, high impedance when OE is low."
      },
      {
        "number": "6",
        "name": "QP2",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 2, high impedance when OE is low."
      },
      {
        "number": "7",
        "name": "QP3",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 3, high impedance when OE is low."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for all voltages (0 V)."
      },
      {
        "number": "9",
        "name": "QS1",
        "type": "output",
        "description": "Serial output taken from the seventh register stage, updated on the positive clock edge, for cascading devices."
      },
      {
        "number": "10",
        "name": "QS2",
        "type": "output",
        "description": "Serial output from the eighth (last) shift register stage, updated on the negative (HIGH-to-LOW) clock edge, for cascading devices."
      },
      {
        "number": "11",
        "name": "QP7",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 7, high impedance when OE is low."
      },
      {
        "number": "12",
        "name": "QP6",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 6, high impedance when OE is low."
      },
      {
        "number": "13",
        "name": "QP5",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 5, high impedance when OE is low."
      },
      {
        "number": "14",
        "name": "QP4",
        "type": "tri_state",
        "description": "Parallel three-state output from storage stage 4, high impedance when OE is low."
      },
      {
        "number": "15",
        "name": "OE",
        "type": "input",
        "description": "Output enable: when high, the parallel outputs QPn are enabled; when low, they are placed in the high-impedance OFF state."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 4.5 V to 5.5 V referenced to GND."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet covers MC74HCT4094A; the MPN given is M74HCT4094ADTR2G. The suffix matches the MC74HCT; Pin numbers were mapped from the Figure 1 pin assignment text, which is extracted without its spatia; The pin assignment is shared by the SOIC-16 and TSSOP-16 variants. The TSSOP-16 outline drawing (pag",
          "3/16 pins cited to the wrong page (name found elsewhere): ['11:QP7@p5', '12:QP6@p5', '14:QP4@p5']"
        ],
        "pages_sent": 12,
        "cost_usd": 0.0666,
        "at": "2026-10-18T22:11:43"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929129345929216",
        "pages": 12,
        "sha256": "954b9b92f2a820bb",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "m74hct4094adtr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "m74hct4094adtr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2d473b8758b8dd5014ae46b120c672b1f324d03eede31ba7d19922bb875d3b08",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}