# M74HCT4094ADTR2G

**onsemi** · Shift Registers · TSSOP-16

M74HCT4094ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input: when high, the data in the 8-bit shift register is transferred to the storage register. |
| 2 | D | input | Serial data input to the shift register, with a minimum set-up time of 10 ns and minimum hold time of 3 ns to CP at VCC = 4.5 V. |
| 3 | CP | input | Clock input: data is shifted on positive (LOW-to-HIGH) clock transitions, with a minimum clock pulse width of 16 ns at VCC = 4.5 V. |
| 4 | QP0 | tri_state | Parallel three-state output from storage stage 0, high impedance when OE is low. |
| 5 | QP1 | tri_state | Parallel three-state output from storage stage 1, high impedance when OE is low. |
| 6 | QP2 | tri_state | Parallel three-state output from storage stage 2, high impedance when OE is low. |
| 7 | QP3 | tri_state | Parallel three-state output from storage stage 3, high impedance when OE is low. |
| 8 | GND | power_in | Ground reference for all voltages (0 V). |
| 9 | QS1 | output | Serial output taken from the seventh register stage, updated on the positive clock edge, for cascading devices. |
| 10 | QS2 | output | Serial output from the eighth (last) shift register stage, updated on the negative (HIGH-to-LOW) clock edge, for cascading devices. |
| 11 | QP7 | tri_state | Parallel three-state output from storage stage 7, high impedance when OE is low. |
| 12 | QP6 | tri_state | Parallel three-state output from storage stage 6, high impedance when OE is low. |
| 13 | QP5 | tri_state | Parallel three-state output from storage stage 5, high impedance when OE is low. |
| 14 | QP4 | tri_state | Parallel three-state output from storage stage 4, high impedance when OE is low. |
| 15 | OE | input | Output enable: when high, the parallel outputs QPn are enabled; when low, they are placed in the high-impedance OFF state. |
| 16 | VCC | power_in | Positive supply, 4.5 V to 5.5 V referenced to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | 4.5 |  | 5.5 | V | Referenced to GND | 4 |
| DC Input/Output Voltage | Vin, Vout | 0 |  |  | V | Referenced to GND; max = VCC | 4 |
| Operating Temperature, All Package Types | TA | -55 |  | 125 | °C | All package types | 4 |
| Input Rise and Fall Time | tr, tf | 0 |  | 500 | ns | Figure 1 | 4 |
| DC Supply Voltage | VCC | -0.5 |  | 7 | V | Referenced to GND | 4 |
| DC Input Voltage | Vin | -0.5 |  |  | V | Referenced to GND; upper limit printed as VCC + 0.5 | 4 |
| DC Output Voltage | Vout | -0.5 |  |  | V | Referenced to GND; upper limit printed as VCC + 0.5 | 4 |
| DC Input Current, per Pin | Iin | -20 |  | 20 | mA | Per pin | 4 |
| DC Output Current, per Pin | Iout | -35 |  | 35 | mA | Per pin | 4 |
| DC Supply Current, VCC and GND Pins | ICC | -75 |  | 75 | mA | VCC and GND pins | 4 |
| Power Dissipation in Still Air, TSSOP Package | PD |  |  | 450 | mW | TSSOP package, still air; derate -6.1 mW/°C from 65 to 125 °C | 4 |
| Storage Temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Minimum High-Level Input Voltage | VIH | 2 |  |  | V | VOUT = 0.1 V or VCC, 0.1 V; /IOUT/ ≤ 20 µA; VCC 4.5 V | 6 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.8 | V | VOUT = 0.1 V or VCC, 0.1 V; /IOUT/ ≤ 20 µA; VCC 4.5 V | 6 |
| Minimum High-Level Output Voltage | VOH | 4.4 |  |  | V | VIN = VIH or VIL; /IOUT/ ≤ 20 µA; VCC 4.5 V | 6 |
| Minimum High-Level Output Voltage | VOH | 5.4 |  |  | V | VIN = VIH or VIL; /IOUT/ ≤ 20 µA; VCC 5.5 V | 6 |
| Minimum High-Level Output Voltage | VOH | 4.1 |  |  | V | VIN = VIH or VIL; /IOUT/ = 6 mA; VCC 4.5 V | 6 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.1 | V | VIN = VIH or VIL; /IOUT/ ≤ 20 µA; VCC 4.5 V | 6 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.4 | V | VIN = VIH or VIL; /IOUT/ = 6 mA; VCC 4.5 V | 6 |
| Maximum Input Leakage Current | IIN | -1 |  | 1 | µA | VIN = VCC or GND; VCC 5.5 V | 6 |
| Maximum Tri-State Output Leakage Current | IOZ | -10 |  | 10 | µA | VIN = VCC or GND; VOUT = VCC or GND; VCC 5.5 V | 6 |
| Maximum Quiescent Supply Current | ICC |  |  | 80 | µA | VIN = VCC or GND; VCC 5.5 V | 6 |
| Additional Quiescent Supply Current | ICC |  |  | 2.9 | mA | VIN = 2.4 V, any one input; VIN = VCC or GND, other inputs; IOUT = 0 A; VCC 5.5 V | 6 |
| Additional Quiescent Supply Current | ICC |  |  | 2.4 | mA | VIN = 2.4 V, any one input; VIN = VCC or GND, other inputs; IOUT = 0 A; VCC 5.5 V | 6 |
| Maximum Propagation Delay CP to QS1 | tPHL, tPLH |  |  | 45 | ns | Figure 7; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum Propagation Delay CP to QS2 | tPHL, tPLH |  |  | 41 | ns | Figure 7; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum Propagation Delay CP to QPn | tPHL, tPLH |  |  | 59 | ns | Figure 7; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum Propagation Delay STR to QPn | tPHL, tPLH |  |  | 54 | ns | Figure 8; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum 3-State Output Enable Time OE to QPn | tPZH, tPZL |  |  | 53 | ns | Figure 9; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum 3-State Output Disable Time OE to QPn | tPHZ, tPLZ |  |  | 38 | ns | Figure 9; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum Output Transition Time | tTHL, tTLH |  |  | 25 | ns | Figure 7; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Clock Pulse Width High or Low | tW | 24 |  |  | ns | Figure 7; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Strobe Pulse Width High | tW | 24 |  |  | ns | Figure 8; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Set-up Time D to CP | tSU | 15 |  |  | ns | Figure 10; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Set-up Time CP to STR | tSU | 30 |  |  | ns | Figure 8; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Hold Time D to CP | th | 3 |  |  | ns | Figure 10; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Hold Time CP to STR | th | 0 |  |  | ns | Figure 8; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Minimum Clock Pulse Frequency | fMAX | 20 |  |  | MHz | Figure 7; tf = tr = 6 ns, CL = 50 pF; VCC 4.5 V | 7 |
| Maximum Input Capacitance | Cin |  |  | 10 | pF |  | 7 |
| Maximum Output Capacitance | Cout |  |  | 15 | pF |  | 7 |

## CAD (KiCad official)

- Symbol: `M74HCT4094ADTR2G`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `m74hct4094adtr2g-etched.step` / `m74hct4094adtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `m74hct4094adtr2g.step` / `m74hct4094adtr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929129345929216) (12 pp, sha256 `954b9b92f2a820bb`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/m74hct4094adtr2g-datasheet.pdf)