component
M74HC14YTTR
Public Made by Adomby adom
STMicroelectronics Inverters, TSSOP-14. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.
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M74HC14YTTR
STMicroelectronics · Inverters · TSSOP-14
M74HC14YTTR from STMicroelectronics, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 2 | 1Y | output | Data output 1Y, the inverted logic output of gate 1 (Y is H when A is L and L when A is H, per the truth table). |
| 3 | 2A | input | Data input 2A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 4 | 2Y | output | Data output 2Y, the inverted logic output of gate 2 (Y is H when A is L and L when A is H, per the truth table). |
| 5 | 3A | input | Data input 3A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 6 | 3Y | output | Data output 3Y, the inverted logic output of gate 3 (Y is H when A is L and L when A is H, per the truth table). |
| 7 | GND | power_in | Ground (0 V) reference for the device. |
| 8 | 4Y | output | Data output 4Y, the inverted logic output of gate 4 (Y is H when A is L and L when A is H, per the truth table). |
| 9 | 4A | input | Data input 4A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 10 | 5Y | output | Data output 5Y, the inverted logic output of gate 5 (Y is H when A is L and L when A is H, per the truth table). |
| 11 | 5A | input | Data input 5A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 12 | 6Y | output | Data output 6Y, the inverted logic output of gate 6 (Y is H when A is L and L when A is H, per the truth table). |
| 13 | 6A | input | Data input 6A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 14 | VCC | power_in | Positive supply voltage; the recommended operating range is 2 to 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 5 | ||
| DC input diode current | IIK | -20 | 20 | mA | 5 | ||
| DC output current | IO | -25 | 25 | mA | 5 | ||
| DC VCC or ground current | ICC or IGND | -50 | 50 | mA | 5 | ||
| Power dissipation | PD | 500 | mW | Note 1: 500 mW at 65 °C; derate to 300 mW by 10 mW/°C from 65 °C to 85 °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Lead temperature | TL | 300 | °C | 10 s | 5 | ||
| Supply voltage (recommended operating) | VCC | 2 | 6 | V | 5 | ||
| Input voltage (recommended operating) | VI | 0 | V | range 0 to VCC | 5 | ||
| Operating temperature | Toper | -55 | 125 | °C | 5 | ||
| High-level input voltage | Vt+ | 1 | 1.28 | 1.5 | V | VCC = 2.0 V; limits over -55 to 125 °C | 6 |
| High-level input voltage | Vt+ | 2.3 | 2.8 | 3.15 | V | VCC = 4.5 V; limits over -55 to 125 °C | 6 |
| High-level input voltage | Vt+ | 3 | 3.7 | 4.2 | V | VCC = 6.0 V; limits over -55 to 125 °C | 6 |
| Low-level input voltage | Vt- | 0.3 | 0.74 | 0.9 | V | VCC = 2.0 V; limits over -55 to 125 °C | 6 |
| Low-level input voltage | Vt- | 1.13 | 1.8 | 2 | V | VCC = 4.5 V; limits over -55 to 125 °C | 6 |
| Low-level input voltage | Vt- | 1.5 | 2.4 | 2.6 | V | VCC = 6.0 V; limits over -55 to 125 °C | 6 |
| Hysteresis voltage | VH | 0.3 | 0.54 | 1 | V | VCC = 2.0 V; limits over -55 to 125 °C | 6 |
| Hysteresis voltage | VH | 0.6 | 1 | 1.4 | V | VCC = 4.5 V; limits over -55 to 125 °C | 6 |
| Hysteresis voltage | VH | 0.8 | 1.3 | 1.7 | V | VCC = 6.0 V; limits over -55 to 125 °C | 6 |
| High-level output voltage | VOH | 1.9 | 2 | V | VCC = 2.0 V, IO = -20 µA; min over -55 to 125 °C | 6 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | VCC = 4.5 V, IO = -20 µA; min over -55 to 125 °C | 6 | |
| High-level output voltage | VOH | 5.9 | 6 | V | VCC = 6.0 V, IO = -20 µA; min over -55 to 125 °C | 6 | |
| High-level output voltage | VOH | 4.1 | 4.31 | V | VCC = 4.5 V, IO = -4.0 mA; min over -55 to 125 °C | 6 | |
| High-level output voltage | VOH | 5.6 | 5.8 | V | VCC = 6.0 V, IO = -5.2 mA; min over -55 to 125 °C | 6 | |
| Low-level output voltage | VOL | 0 | 0.1 | V | VCC = 2.0 V, IO = -20 µA; max over -55 to 125 °C | 6 | |
| Low-level output voltage | VOL | 0.17 | 0.4 | V | VCC = 4.5 V, IO = -4.0 mA; max over -55 to 125 °C | 6 | |
| Low-level output voltage | VOL | 0.18 | 0.4 | V | VCC = 6.0 V, IO = -5.2 mA; max over -55 to 125 °C | 6 | |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VCC = 6.0 V, VI = VCC or GND; limits over -55 to 125 °C | 6 |
| Quiescent supply current | ICC | 20 | µA | max over -55 to 125 °C | 6 | ||
| Output transition time | tTLH, tTHL | 30 | 110 | ns | VCC = 2.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 | |
| Output transition time | tTLH, tTHL | 8 | 22 | ns | VCC = 4.5 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 | |
| Output transition time | tTLH, tTHL | 7 | 19 | ns | VCC = 6.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 | |
| Propagation delay time | tPLH, tPHL | 42 | 190 | ns | VCC = 2.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 | |
| Propagation delay time | tPLH, tPHL | 14 | 38 | ns | VCC = 4.5 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 | |
| Propagation delay time | tPLH, tPHL | 12 | 32 | ns | VCC = 6.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 | |
| Input capacitance | CIN | 5 | 10 | pF | VCC = 5.0 V; max over -55 to 125 °C | 7 |
CAD (KiCad official)
- Symbol:
M74HC14YTTR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
m74hc14yttr-etched.step/m74hc14yttr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);m74hc14yttr.step/m74hc14yttr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (15 pp, sha256
bfc8ae82393e0d60, retrieved 2026-11-05, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# M74HC14YTTR
**STMicroelectronics** · Inverters · TSSOP-14
M74HC14YTTR from STMicroelectronics, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 2 | 1Y | output | Data output 1Y, the inverted logic output of gate 1 (Y is H when A is L and L when A is H, per the truth table). |
| 3 | 2A | input | Data input 2A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 4 | 2Y | output | Data output 2Y, the inverted logic output of gate 2 (Y is H when A is L and L when A is H, per the truth table). |
| 5 | 3A | input | Data input 3A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 6 | 3Y | output | Data output 3Y, the inverted logic output of gate 3 (Y is H when A is L and L when A is H, per the truth table). |
| 7 | GND | power_in | Ground (0 V) reference for the device. |
| 8 | 4Y | output | Data output 4Y, the inverted logic output of gate 4 (Y is H when A is L and L when A is H, per the truth table). |
| 9 | 4A | input | Data input 4A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 10 | 5Y | output | Data output 5Y, the inverted logic output of gate 5 (Y is H when A is L and L when A is H, per the truth table). |
| 11 | 5A | input | Data input 5A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 12 | 6Y | output | Data output 6Y, the inverted logic output of gate 6 (Y is H when A is L and L when A is H, per the truth table). |
| 13 | 6A | input | Data input 6A of the hex Schmitt inverter; per the datasheet, all inputs have a 20 % VCC hysteresis level. |
| 14 | VCC | power_in | Positive supply voltage; the recommended operating range is 2 to 6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | | 7 | V | | 5 |
| DC input diode current | IIK | -20 | | 20 | mA | | 5 |
| DC output current | IO | -25 | | 25 | mA | | 5 |
| DC VCC or ground current | ICC or IGND | -50 | | 50 | mA | | 5 |
| Power dissipation | PD | | | 500 | mW | Note 1: 500 mW at 65 °C; derate to 300 mW by 10 mW/°C from 65 °C to 85 °C | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| Lead temperature | TL | | | 300 | °C | 10 s | 5 |
| Supply voltage (recommended operating) | VCC | 2 | | 6 | V | | 5 |
| Input voltage (recommended operating) | VI | 0 | | | V | range 0 to VCC | 5 |
| Operating temperature | Toper | -55 | | 125 | °C | | 5 |
| High-level input voltage | Vt+ | 1 | 1.28 | 1.5 | V | VCC = 2.0 V; limits over -55 to 125 °C | 6 |
| High-level input voltage | Vt+ | 2.3 | 2.8 | 3.15 | V | VCC = 4.5 V; limits over -55 to 125 °C | 6 |
| High-level input voltage | Vt+ | 3 | 3.7 | 4.2 | V | VCC = 6.0 V; limits over -55 to 125 °C | 6 |
| Low-level input voltage | Vt- | 0.3 | 0.74 | 0.9 | V | VCC = 2.0 V; limits over -55 to 125 °C | 6 |
| Low-level input voltage | Vt- | 1.13 | 1.8 | 2 | V | VCC = 4.5 V; limits over -55 to 125 °C | 6 |
| Low-level input voltage | Vt- | 1.5 | 2.4 | 2.6 | V | VCC = 6.0 V; limits over -55 to 125 °C | 6 |
| Hysteresis voltage | VH | 0.3 | 0.54 | 1 | V | VCC = 2.0 V; limits over -55 to 125 °C | 6 |
| Hysteresis voltage | VH | 0.6 | 1 | 1.4 | V | VCC = 4.5 V; limits over -55 to 125 °C | 6 |
| Hysteresis voltage | VH | 0.8 | 1.3 | 1.7 | V | VCC = 6.0 V; limits over -55 to 125 °C | 6 |
| High-level output voltage | VOH | 1.9 | 2 | | V | VCC = 2.0 V, IO = -20 µA; min over -55 to 125 °C | 6 |
| High-level output voltage | VOH | 4.4 | 4.5 | | V | VCC = 4.5 V, IO = -20 µA; min over -55 to 125 °C | 6 |
| High-level output voltage | VOH | 5.9 | 6 | | V | VCC = 6.0 V, IO = -20 µA; min over -55 to 125 °C | 6 |
| High-level output voltage | VOH | 4.1 | 4.31 | | V | VCC = 4.5 V, IO = -4.0 mA; min over -55 to 125 °C | 6 |
| High-level output voltage | VOH | 5.6 | 5.8 | | V | VCC = 6.0 V, IO = -5.2 mA; min over -55 to 125 °C | 6 |
| Low-level output voltage | VOL | | 0 | 0.1 | V | VCC = 2.0 V, IO = -20 µA; max over -55 to 125 °C | 6 |
| Low-level output voltage | VOL | | 0.17 | 0.4 | V | VCC = 4.5 V, IO = -4.0 mA; max over -55 to 125 °C | 6 |
| Low-level output voltage | VOL | | 0.18 | 0.4 | V | VCC = 6.0 V, IO = -5.2 mA; max over -55 to 125 °C | 6 |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VCC = 6.0 V, VI = VCC or GND; limits over -55 to 125 °C | 6 |
| Quiescent supply current | ICC | | | 20 | µA | max over -55 to 125 °C | 6 |
| Output transition time | tTLH, tTHL | | 30 | 110 | ns | VCC = 2.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 |
| Output transition time | tTLH, tTHL | | 8 | 22 | ns | VCC = 4.5 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 |
| Output transition time | tTLH, tTHL | | 7 | 19 | ns | VCC = 6.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 |
| Propagation delay time | tPLH, tPHL | | 42 | 190 | ns | VCC = 2.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 |
| Propagation delay time | tPLH, tPHL | | 14 | 38 | ns | VCC = 4.5 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 |
| Propagation delay time | tPLH, tPHL | | 12 | 32 | ns | VCC = 6.0 V, CL = 50 pF, tr = tf = 6 ns; max over -55 to 125 °C | 6 |
| Input capacitance | CIN | | 5 | 10 | pF | VCC = 5.0 V; max over -55 to 125 °C | 7 |
## CAD (KiCad official)
- Symbol: `M74HC14YTTR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `m74hc14yttr-etched.step` / `m74hc14yttr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `m74hc14yttr.step` / `m74hc14yttr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/m74hc14yttr.pdf) (15 pp, sha256 `bfc8ae82393e0d60`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/m74hc14yttr-datasheet.pdf)