component

M74HC132YRM13TR

Public Made by Adom

by adom

STMicroelectronics Logic Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogicm74hc132yrm13tr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs m74hc132yrm13tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers m74hc132yrm13tr: viewers · Ray 1mo ago
m74hc132yrm13tr-etched.fit.json m74hc132yrm13tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
m74hc132yrm13tr-etched.glb m74hc132yrm13tr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 13d ago
m74hc132yrm13tr-etched.step m74hc132yrm13tr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 13d ago
m74hc132yrm13tr.glb Publish 0.1.0 · Ray 1mo ago
m74hc132yrm13tr.kicad_mod Publish 0.1.0 · Ray 1mo ago
m74hc132yrm13tr.kicad_sym Publish 0.1.0 · Ray 1mo ago
m74hc132yrm13tr.lbr Publish 0.1.0 · Ray 1mo ago
m74hc132yrm13tr.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json m74hc132yrm13tr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray 13d ago
README.md m74hc132yrm13tr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

M74HC132YRM13TR

STMicroelectronics · Logic Gates · SOIC-14

M74HC132YRM13TR from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 Schmitt-trigger data input A. Input voltage range 0 V to VCC; hysteresis VH ≈ 0.9 V typ at VCC = 5 V. Input leakage ±1 µA max.
2 1B input Gate 1 Schmitt-trigger data input B. Second input of NAND gate 1. Hysteresis ~20% VCC.
3 1Y output Gate 1 NAND output (Y = NAND(1A,1B)). Symmetrical CMOS output;
4 2A input Gate 2 Schmitt-trigger data input A.
5 2B input Gate 2 Schmitt-trigger data input B.
6 2Y output Gate 2 NAND output (Y = NAND(2A,2B)). CMOS push-pull, 4 mA drive.
7 GND power_in Ground (0 V) reference for the device. Connect to system ground with a low-impedance path.
8 3Y output Gate 3 NAND output (Y = NAND(3A,3B)).
9 3A input Gate 3 Schmitt-trigger data input A.
10 3B input Gate 3 Schmitt-trigger data input B.
11 4Y output Gate 4 NAND output (Y = NAND(4A,4B)).
12 4A input Gate 4 Schmitt-trigger data input A.
13 4B input Gate 4 Schmitt-trigger data input B.
14 VCC power_in Positive supply voltage. Recommended VCC = 2 V to 6 V (absolute max -0.5 V to +7 V). Decouple locally with a 100 nF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • M74HC132RM13TR
  • M74HC132YRM13TR
  • M74HC132TTR
  • M74HC132YTTR

CAD (KiCad official)

  • Symbol: M74HC132YRM13TR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: m74hc132yrm13tr-etched.step / m74hc132yrm13tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m74hc132yrm13tr.step / m74hc132yrm13tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 2c8ff2336ace41f2, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF