M252SE3AE

Nuvoton Tech · Microcontrollers (MCU/MPU/SOC) · LQFP-64(7x7)

M252SE3AE from Nuvoton Tech, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PB.6	bidirectional	GPIO PB.6 multiplexed with EADC0_CH6, EBI_nWRH, USCI1_DAT1, UART1_RXD, EBI_nCS1, BPWM1_CH5, PWM1_BRAKE1, PWM1_CH5, INT4 and ACMP1_O.
2	PB.5	bidirectional	GPIO PB.5 multiplexed with EADC0_CH5, ACMP1_N, EBI_ADR0, I2C0_SCL, USCI1_CTL0, SC0_CLK, PWM0_CH0, PSIO0_CH4, UART2_TXD, TM0 and INT0.
3	PB.4	bidirectional	GPIO PB.4 multiplexed with EADC0_CH4, ACMP1_P1, EBI_ADR1, I2C0_SDA, USCI1_CTL1, SC0_DAT, PWM0_CH1, PSIO0_CH5, UART2_RXD, TM1 and INT1.
4	PB.3	bidirectional	GPIO PB.3 multiplexed with EADC0_CH3, ACMP0_N, EBI_ADR2, I2C1_SCL, UART1_TXD, USCI1_DAT1, SC0_RST, PWM0_CH2, PSIO0_CH6, PWM0_BRAKE0, TM2 and INT2.
5	PB.2	bidirectional	GPIO PB.2 multiplexed with EADC0_CH2, ACMP0_P1, EBI_ADR3, I2C1_SDA, UART1_RXD, USCI1_DAT0, SC0_PWR, PWM0_CH3, PSIO0_CH7, TM3 and INT3.
6	PB.1	bidirectional	GPIO PB.1 multiplexed with EADC0_CH1, EBI_ADR8, UART2_TXD, USCI1_CLK, I2C1_SCL, QSPI0_MISO1, PWM0_CH4, PWM1_CH4 and PWM0_BRAKE0.
7	PB.0	bidirectional	GPIO PB.0 multiplexed with EADC0_CH0, EBI_ADR9, UART2_RXD, SPI0_I2SMCLK, I2C1_SDA, QSPI0_MOSI1, PWM0_CH5, PWM1_CH5 and PWM0_BRAKE1.
8	PA.11	bidirectional	GPIO PA.11 multiplexed with ACMP0_P0, EBI_nRD, USCI0_CLK, BPWM0_CH0 and TM0_EXT.
9	PA.10	bidirectional	GPIO PA.10 multiplexed with ACMP1_P0, EBI_nWR, USCI0_DAT0, BPWM0_CH1 and TM1_EXT.
10	PA.9	bidirectional	GPIO PA.9 multiplexed with EBI_MCLK, USCI0_DAT1, UART1_TXD, BPWM0_CH2 and TM2_EXT.
11	PA.8	bidirectional	GPIO PA.8 multiplexed with EBI_ALE, USCI0_CTL1, UART1_RXD, BPWM0_CH3, TM3_EXT and INT4.
12	PF.6	bidirectional	GPIO PF.6 multiplexed with EBI_ADR19, SC0_CLK, SPI0_MOSI, EBI_nCS0 and TAMPER0.
13	VBAT	power_in	Power supply by batteries for RTC.
14	PF.5	bidirectional	GPIO PF.5 multiplexed with UART2_RXD, UART2_nCTS, PWM0_CH0, BPWM0_CH4, X32_IN (32.768 kHz crystal input) and EADC0_ST.
15	PF.4	bidirectional	GPIO PF.4 multiplexed with UART2_TXD, UART2_nRTS, PWM0_CH1, BPWM0_CH5 and X32_OUT (32.768 kHz crystal output).
16	PF.3	bidirectional	GPIO PF.3 multiplexed with EBI_nCS0, UART0_TXD, I2C0_SCL, XT1_IN (external high speed crystal input) and BPWM1_CH0.
17	PF.2	bidirectional	GPIO PF.2 multiplexed with EBI_nCS1, UART0_RXD, I2C0_SDA, QSPI0_CLK, XT1_OUT (external high speed crystal output) and BPWM1_CH1.
18	PC.7	bidirectional	GPIO PC.7 multiplexed with EBI_AD9, UART0_nCTS, I2C1_SMBAL, PWM1_CH2, BPWM1_CH0, TM0 and INT3.
19	PC.6	bidirectional	GPIO PC.6 multiplexed with EBI_AD8, UART0_nRTS, I2C1_SMBSUS, PWM1_CH3, BPWM1_CH1, TM1 and INT2.
20	PA.7	bidirectional	GPIO PA.7 multiplexed with EBI_AD7, UART0_TXD, I2C1_SCL, PWM1_CH4, BPWM1_CH2, ACMP0_WLAT, TM2 and INT1.
21	PA.6	bidirectional	GPIO PA.6 multiplexed with EBI_AD6, UART0_RXD, I2C1_SDA, PWM1_CH5, BPWM1_CH3, ACMP1_WLAT, TM3 and INT0.
22	VSS	power_in	Ground pin for digital circuit.
23	VDD	power_in	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
24	PD.15	bidirectional	GPIO PD.15 multiplexed with PSIO0_CH7, PWM0_CH5, TM3 and INT1.
25	PA.5	bidirectional	GPIO PA.5 (powered from VDDIO) multiplexed with QSPI0_MISO1, UART0_nCTS, UART0_TXD, I2C0_SCL, BPWM0_CH5 and PWM0_CH0.
26	PA.4	bidirectional	GPIO PA.4 (powered from VDDIO) multiplexed with QSPI0_MOSI1, SPI0_I2SMCLK, SC0_nCD, UART0_nRTS, UART0_RXD, I2C0_SDA, USCI2_CTL1, BPWM0_CH4 and PWM0_CH1.
27	PA.3	bidirectional	GPIO PA.3 (powered from VDDIO) multiplexed with QSPI0_SS, SPI0_SS, SC0_PWR, I2C0_SMBAL, UART1_TXD, I2C1_SCL, PSIO0_CH4, USCI2_CTL0, BPWM0_CH3, PWM0_CH2, CLKO and PWM1_BRAKE1.
28	PA.2	bidirectional	GPIO PA.2 (powered from VDDIO) multiplexed with QSPI0_CLK, SPI0_CLK, SC0_RST, I2C0_SMBSUS, UART1_RXD, I2C1_SDA, PSIO0_CH5, USCI2_CLK, BPWM0_CH2 and PWM0_CH3.
29	PA.1	bidirectional	GPIO PA.1 (powered from VDDIO) multiplexed with QSPI0_MISO0, SPI0_MISO, SC0_DAT, UART0_TXD, UART1_nCTS, PSIO0_CH6, USCI2_DAT0, BPWM0_CH1 and PWM0_CH4.
30	PA.0	bidirectional	GPIO PA.0 (powered from VDDIO) multiplexed with QSPI0_MOSI0, SPI0_MOSI, SC0_CLK, UART0_RXD, UART1_nRTS, PSIO0_CH7, USCI2_DAT1, BPWM0_CH0 and PWM0_CH5.
31	VDDIO	power_in	Power supply for PA.0~PA.5.
32	nRESET	input	External reset input, active LOW with internal pull-up; a 10 kΩ pull-up resistor and 10 uF capacitor are recommended.
33	PF.0	bidirectional	GPIO PF.0 multiplexed with UART1_TXD, I2C1_SCL, UART0_TXD, BPWM1_CH0 and ICE_DAT (serial wired debugger data; 100 kΩ pull-up recommended).
34	PF.1	bidirectional	GPIO PF.1 multiplexed with UART1_RXD, I2C1_SDA, UART0_RXD, BPWM1_CH1 and ICE_CLK (serial wired debugger clock; 100 kΩ pull-up recommended).
35	PC.5	bidirectional	GPIO PC.5 multiplexed with EBI_AD5, QSPI0_MISO1, UART2_TXD, I2C1_SCL, PWM1_CH0 and PSIO0_CH0.
36	PC.4	bidirectional	GPIO PC.4 multiplexed with EBI_AD4, QSPI0_MOSI1, UART2_RXD, I2C1_SDA, PWM1_CH1, USCI2_CTL1 and PSIO0_CH1.
37	PC.3	bidirectional	GPIO PC.3 multiplexed with EBI_AD3, QSPI0_SS, UART2_nRTS, I2C0_SMBAL, PWM1_CH2, USCI2_CTL0 and PSIO0_CH2.
38	PC.2	bidirectional	GPIO PC.2 multiplexed with EBI_AD2, QSPI0_CLK, UART2_nCTS, I2C0_SMBSUS, PWM1_CH3, USCI2_CLK and PSIO0_CH3.
39	PC.1	bidirectional	GPIO PC.1 multiplexed with EBI_AD1, QSPI0_MISO0, UART2_TXD, I2C0_SCL, PWM1_CH4, USCI2_DAT0 and ACMP0_O.
40	PC.0	bidirectional	GPIO PC.0 multiplexed with EBI_AD0, QSPI0_MOSI0, UART2_RXD, I2C0_SDA, PWM1_CH5, USCI2_DAT1 and ACMP1_O.
41	PD.3	bidirectional	GPIO PD.3 multiplexed with EBI_AD10, USCI0_CTL1, SPI0_SS, USCI1_CTL0 and UART0_TXD.
42	PD.2	bidirectional	GPIO PD.2 multiplexed with EBI_AD11, USCI0_DAT1, SPI0_CLK and UART0_RXD.
43	PD.1	bidirectional	GPIO PD.1 multiplexed with EBI_AD12, USCI0_DAT0 and SPI0_MISO.
44	PD.0	bidirectional	GPIO PD.0 multiplexed with EBI_AD13, USCI0_CLK, SPI0_MOSI and TM2.
45	USB_VBUS	power_in	Power supply from USB host or HUB.
46	USB_D-	bidirectional	USB differential signal D-.
47	USB_D+	bidirectional	USB differential signal D+.
48	USB_VDD33_CAP	passive	Internal power regulator output 3.3V decoupling pin.
49	VSS	power_in	Ground pin for digital circuit.
50	LDO_CAP	passive	LDO output pin; needs to be connected with a 1uF capacitor.
51	VDD	power_in	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
52	PC.14	bidirectional	GPIO PC.14 multiplexed with EBI_AD11, SPI0_I2SMCLK, USCI0_CTL0, QSPI0_CLK, USCI2_CLK and TM1.
53	PB.15	bidirectional	GPIO PB.15 multiplexed with EADC0_CH15, EBI_AD12, SPI0_SS, USCI0_CTL1, UART0_nCTS, PSIO0_CH0, PWM1_CH0, TM0_EXT and PWM0_BRAKE1.
54	PB.14	bidirectional	GPIO PB.14 multiplexed with EADC0_CH14, EBI_AD13, SPI0_CLK, USCI0_DAT1, UART0_nRTS, PSIO0_CH1, PWM1_CH1, TM1_EXT and CLKO.
55	PB.13	bidirectional	GPIO PB.13 multiplexed with EADC0_CH13, ACMP0_P3, ACMP1_P3, EBI_AD14, SPI0_MISO, USCI0_DAT0, UART0_TXD, PSIO0_CH2, PWM1_CH2 and TM2_EXT.
56	PB.12	bidirectional	GPIO PB.12 multiplexed with EADC0_CH12, ACMP0_P2, ACMP1_P2, EBI_AD15, SPI0_MOSI, USCI0_CLK, UART0_RXD, PSIO0_CH3, PWM1_CH3 and TM3_EXT.
57	AVDD	power_in	Power supply for internal analog circuit.
58	VREF	power_in	ADC reference voltage input; needs to be connected with a 1uF capacitor.
59	AVSS	power_in	Ground pin for analog circuit.
60	PB.11	bidirectional	GPIO PB.11 multiplexed with EADC0_CH11, EBI_ADR16, UART0_nCTS, I2C1_SCL, SPI0_I2SMCLK and BPWM1_CH0.
61	PB.10	bidirectional	GPIO PB.10 multiplexed with EADC0_CH10, EBI_ADR17, USCI1_CTL0, UART0_nRTS, I2C1_SDA and BPWM1_CH1.
62	PB.9	bidirectional	GPIO PB.9 multiplexed with EADC0_CH9, EBI_ADR18, USCI1_CTL1, UART0_TXD, UART1_nCTS, I2C1_SMBAL and BPWM1_CH2.
63	PB.8	bidirectional	GPIO PB.8 multiplexed with EADC0_CH8, EBI_ADR19, USCI1_CLK, UART0_RXD, UART1_nRTS, I2C1_SMBSUS and BPWM1_CH3.
64	PB.7	bidirectional	GPIO PB.7 multiplexed with EADC0_CH7, EBI_nWRL, USCI1_DAT0, UART1_TXD, EBI_nCS0, BPWM1_CH4, PWM1_BRAKE0, PWM1_CH4, INT5 and ACMP0_O.

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	LQFP-64(7x7)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC power supply	VDD-VSS	-0.3		6.5	V		197
VDDIO power supply	VDDIO-VSS	-0.3		6.5	V		197
VBAT power supply	VBAT-VSS	-0.3		6.5	V		197
Input voltage on any other pin	VIN	-0.3		6.5	V	VSS-0.3 to 6.5 V	197
Maximum current into VDD	ΣIDD			200	mA		198
Maximum current out of VSS	ΣISS			100	mA		198
Maximum current sunk by an I/O pin	IIO			20	mA		198
Maximum current sourced by an I/O pin	IIO			20	mA		198
Maximum injected current by an I/O pin	IINJ(PIN)	-5		5	mA		198
Maximum injected current by total I/O pins	ΣIINJ(PIN)	-25		25	mA		198
Operating ambient temperature	TA	-40		105	℃		204
Operating junction temperature	TJ	-40		125	℃		199
Storage temperature	TST	-65		150	℃		199
Thermal resistance junction-ambient, 64-pin LQFP(7x7 mm)	θJA		58		℃/Watt	JESD51-2	199
ESD human body model	VHBM	-6000		6000	V		201
ESD charge device model	VCDM	-500		500	V		201
Latch-up pin current	LU	-150		150	mA	Class I	201
Operation voltage	VDD	1.75		5.5	V		204
VDDIO operation voltage	VDDIO	1.65		5.5	V		204
VBAT operation voltage	VBAT	1.75		5.5	V		204
Internal AHB clock frequency	fHCLK			48	MHz		204
ESR of CLDO output capacitor	RESR			0.5	Ω		204
Band-gap voltage	VBG	795	815	840	mV		204
LDO output voltage	VLDO		1.5		V		204
Inrush current on voltage regulator power-on	IRUSH		60	150	mA		204
Normal run current, peripherals disabled	IDD_RUN		6.2	7.35	mA	PL0, from Flash, all peripherals disable, HIRC/PLL/HXT, 48 MHz; typ TA=25 °C, max TA=105 °C	208
Normal run current, peripherals enabled	IDD_RUN		17.5	20	mA	PL0, from Flash, all peripherals enable, HIRC/PLL/HXT, 48 MHz; typ TA=25 °C, max TA=105 °C	208
Idle current, peripherals disabled	IDD_IDLE		2.4	3.05	mA	PL0, all peripherals disable, HIRC/PLL/HXT, 48 MHz; typ TA=25 °C, max TA=105 °C	209
Wakeup from IDLE mode	tWU_IDLE		5	6	cycles	48 MHz HIRC	212
Wakeup from deep Power-down mode	tWU_DPD		190	250	µS		212
Wakeup from normal Power-down mode	tWU_NPD		19	30	µS		212
Wakeup from fast wake up Power-down mode	tWU_FWPD		12	15	µS		212
Input low voltage (Schmitt trigger)	VIL	0		0.3	V	max is 0.3*VDD	213
Input high voltage (Schmitt trigger)	VIH	0.7			V	min is 0.7*VDD, max VDD	213
Input leakage current	ILK	-1		1	A	VSS < VIN < VDD, Open-drain or input only mode	213
Pull up resistor	RPU	45	52	57	kΩ		213
Pull down resistor	RPD	45	52	57	kΩ		213
Source current push-pull high level	ISR	-5	-8	-10.5	mA	VDD = 4.5 V, VIN=(VDD-0.4) V	214
Sink current push-pull low level	ISK	13	20	27	mA	VDD = 4.5 V, VIN= 0.4 V	214
I/O pin capacitance	CIO		5		pF		214
Internal nRESET pull up resistor	RRST	45	53	47	kΩ		215
HIRC oscillator frequency	fHRC	47.52	48	48.48	MHz	TA = 25 °C, VDD = 3.3V	216
HIRC frequency drift over temperature and voltage		-2.8		2.8	%	TA = -40C ~ +105 °C, VDD = 1.75 ~ 5.5V	216
MIRC oscillator frequency	FMRC	3.951	4.032	4.112	MHz	TA = 25 °C, VDD = 3.3V	217
MIRC frequency drift over temperature and voltage		-10		10	%	TA = -40C ~ +105 °C, VDD = 1.75 ~ 5.5V	217
LIRC frequency drift over temperature and voltage		-15		15	%	TA=-40~~105°C, VDD=1.75V~~5.5V, Without software calibration	218
POR reset voltage	VPOR	1.4	1.5	1.65	V		230
LVR reset voltage	VLVR	1.55	1.6	1.7	V		230
BOD brown-out detect voltage (falling edge)	VBOD	2.9	3	3.1	V	BODVL = 5	230
ADC analog operating voltage	AVDD	1.75		5.5	V	VDD = AVDD	232
ADC integral non-linearity error	INL	-3		3	LSB	VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28	232
ADC differential non-linearity error	DNL	-1		3	LSB	VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28	232
ADC gain error	EG	-6		6	LSB	VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28	232
ADC offset error	EO	-3		3	LSB	VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28	232
ADC absolute error	EA	-1.5		6.5	LSB	VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28	232
ADC sampling rate	FSPS	250		730	kSPS	FSPS = FADC / TCONV	232
Internal reference voltage	VREF_INT	2.97	3.072	3.17	V	AVDD >= 3.4 V	239
Temperature sensor offset voltage	VTEMP_OS	690	720	750	mV	TA = 0°C	240
Temperature sensor temperature coefficient	TC	-1.74	-1.83	-1.9	mV/°C		240
Flash endurance	NENDUR	20000			cycles		252
Flash data retention	TRET	10			year	20 kcycle, TJ = 125℃	252

CAD (KiCad official)

Symbol: M252SE3AE
Footprint: Package_QFP:LQFP-64_7x7mm_P0.4mm
3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
3D model files: m252se3ae-etched.step / m252se3ae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m252se3ae.step / m252se3ae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (263 pp, sha256 5adaa62150d5740c, retrieved 2026-10-23, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# M252SE3AE

**Nuvoton Tech** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(7x7)

M252SE3AE from Nuvoton Tech, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB.6 | bidirectional | GPIO PB.6 multiplexed with EADC0_CH6, EBI_nWRH, USCI1_DAT1, UART1_RXD, EBI_nCS1, BPWM1_CH5, PWM1_BRAKE1, PWM1_CH5, INT4 and ACMP1_O. |
| 2 | PB.5 | bidirectional | GPIO PB.5 multiplexed with EADC0_CH5, ACMP1_N, EBI_ADR0, I2C0_SCL, USCI1_CTL0, SC0_CLK, PWM0_CH0, PSIO0_CH4, UART2_TXD, TM0 and INT0. |
| 3 | PB.4 | bidirectional | GPIO PB.4 multiplexed with EADC0_CH4, ACMP1_P1, EBI_ADR1, I2C0_SDA, USCI1_CTL1, SC0_DAT, PWM0_CH1, PSIO0_CH5, UART2_RXD, TM1 and INT1. |
| 4 | PB.3 | bidirectional | GPIO PB.3 multiplexed with EADC0_CH3, ACMP0_N, EBI_ADR2, I2C1_SCL, UART1_TXD, USCI1_DAT1, SC0_RST, PWM0_CH2, PSIO0_CH6, PWM0_BRAKE0, TM2 and INT2. |
| 5 | PB.2 | bidirectional | GPIO PB.2 multiplexed with EADC0_CH2, ACMP0_P1, EBI_ADR3, I2C1_SDA, UART1_RXD, USCI1_DAT0, SC0_PWR, PWM0_CH3, PSIO0_CH7, TM3 and INT3. |
| 6 | PB.1 | bidirectional | GPIO PB.1 multiplexed with EADC0_CH1, EBI_ADR8, UART2_TXD, USCI1_CLK, I2C1_SCL, QSPI0_MISO1, PWM0_CH4, PWM1_CH4 and PWM0_BRAKE0. |
| 7 | PB.0 | bidirectional | GPIO PB.0 multiplexed with EADC0_CH0, EBI_ADR9, UART2_RXD, SPI0_I2SMCLK, I2C1_SDA, QSPI0_MOSI1, PWM0_CH5, PWM1_CH5 and PWM0_BRAKE1. |
| 8 | PA.11 | bidirectional | GPIO PA.11 multiplexed with ACMP0_P0, EBI_nRD, USCI0_CLK, BPWM0_CH0 and TM0_EXT. |
| 9 | PA.10 | bidirectional | GPIO PA.10 multiplexed with ACMP1_P0, EBI_nWR, USCI0_DAT0, BPWM0_CH1 and TM1_EXT. |
| 10 | PA.9 | bidirectional | GPIO PA.9 multiplexed with EBI_MCLK, USCI0_DAT1, UART1_TXD, BPWM0_CH2 and TM2_EXT. |
| 11 | PA.8 | bidirectional | GPIO PA.8 multiplexed with EBI_ALE, USCI0_CTL1, UART1_RXD, BPWM0_CH3, TM3_EXT and INT4. |
| 12 | PF.6 | bidirectional | GPIO PF.6 multiplexed with EBI_ADR19, SC0_CLK, SPI0_MOSI, EBI_nCS0 and TAMPER0. |
| 13 | VBAT | power_in | Power supply by batteries for RTC. |
| 14 | PF.5 | bidirectional | GPIO PF.5 multiplexed with UART2_RXD, UART2_nCTS, PWM0_CH0, BPWM0_CH4, X32_IN (32.768 kHz crystal input) and EADC0_ST. |
| 15 | PF.4 | bidirectional | GPIO PF.4 multiplexed with UART2_TXD, UART2_nRTS, PWM0_CH1, BPWM0_CH5 and X32_OUT (32.768 kHz crystal output). |
| 16 | PF.3 | bidirectional | GPIO PF.3 multiplexed with EBI_nCS0, UART0_TXD, I2C0_SCL, XT1_IN (external high speed crystal input) and BPWM1_CH0. |
| 17 | PF.2 | bidirectional | GPIO PF.2 multiplexed with EBI_nCS1, UART0_RXD, I2C0_SDA, QSPI0_CLK, XT1_OUT (external high speed crystal output) and BPWM1_CH1. |
| 18 | PC.7 | bidirectional | GPIO PC.7 multiplexed with EBI_AD9, UART0_nCTS, I2C1_SMBAL, PWM1_CH2, BPWM1_CH0, TM0 and INT3. |
| 19 | PC.6 | bidirectional | GPIO PC.6 multiplexed with EBI_AD8, UART0_nRTS, I2C1_SMBSUS, PWM1_CH3, BPWM1_CH1, TM1 and INT2. |
| 20 | PA.7 | bidirectional | GPIO PA.7 multiplexed with EBI_AD7, UART0_TXD, I2C1_SCL, PWM1_CH4, BPWM1_CH2, ACMP0_WLAT, TM2 and INT1. |
| 21 | PA.6 | bidirectional | GPIO PA.6 multiplexed with EBI_AD6, UART0_RXD, I2C1_SDA, PWM1_CH5, BPWM1_CH3, ACMP1_WLAT, TM3 and INT0. |
| 22 | VSS | power_in | Ground pin for digital circuit. |
| 23 | VDD | power_in | Power supply for I/O ports and LDO source for internal PLL and digital circuit. |
| 24 | PD.15 | bidirectional | GPIO PD.15 multiplexed with PSIO0_CH7, PWM0_CH5, TM3 and INT1. |
| 25 | PA.5 | bidirectional | GPIO PA.5 (powered from VDDIO) multiplexed with QSPI0_MISO1, UART0_nCTS, UART0_TXD, I2C0_SCL, BPWM0_CH5 and PWM0_CH0. |
| 26 | PA.4 | bidirectional | GPIO PA.4 (powered from VDDIO) multiplexed with QSPI0_MOSI1, SPI0_I2SMCLK, SC0_nCD, UART0_nRTS, UART0_RXD, I2C0_SDA, USCI2_CTL1, BPWM0_CH4 and PWM0_CH1. |
| 27 | PA.3 | bidirectional | GPIO PA.3 (powered from VDDIO) multiplexed with QSPI0_SS, SPI0_SS, SC0_PWR, I2C0_SMBAL, UART1_TXD, I2C1_SCL, PSIO0_CH4, USCI2_CTL0, BPWM0_CH3, PWM0_CH2, CLKO and PWM1_BRAKE1. |
| 28 | PA.2 | bidirectional | GPIO PA.2 (powered from VDDIO) multiplexed with QSPI0_CLK, SPI0_CLK, SC0_RST, I2C0_SMBSUS, UART1_RXD, I2C1_SDA, PSIO0_CH5, USCI2_CLK, BPWM0_CH2 and PWM0_CH3. |
| 29 | PA.1 | bidirectional | GPIO PA.1 (powered from VDDIO) multiplexed with QSPI0_MISO0, SPI0_MISO, SC0_DAT, UART0_TXD, UART1_nCTS, PSIO0_CH6, USCI2_DAT0, BPWM0_CH1 and PWM0_CH4. |
| 30 | PA.0 | bidirectional | GPIO PA.0 (powered from VDDIO) multiplexed with QSPI0_MOSI0, SPI0_MOSI, SC0_CLK, UART0_RXD, UART1_nRTS, PSIO0_CH7, USCI2_DAT1, BPWM0_CH0 and PWM0_CH5. |
| 31 | VDDIO | power_in | Power supply for PA.0~PA.5. |
| 32 | nRESET | input | External reset input, active LOW with internal pull-up; a 10 kΩ pull-up resistor and 10 uF capacitor are recommended. |
| 33 | PF.0 | bidirectional | GPIO PF.0 multiplexed with UART1_TXD, I2C1_SCL, UART0_TXD, BPWM1_CH0 and ICE_DAT (serial wired debugger data; 100 kΩ pull-up recommended). |
| 34 | PF.1 | bidirectional | GPIO PF.1 multiplexed with UART1_RXD, I2C1_SDA, UART0_RXD, BPWM1_CH1 and ICE_CLK (serial wired debugger clock; 100 kΩ pull-up recommended). |
| 35 | PC.5 | bidirectional | GPIO PC.5 multiplexed with EBI_AD5, QSPI0_MISO1, UART2_TXD, I2C1_SCL, PWM1_CH0 and PSIO0_CH0. |
| 36 | PC.4 | bidirectional | GPIO PC.4 multiplexed with EBI_AD4, QSPI0_MOSI1, UART2_RXD, I2C1_SDA, PWM1_CH1, USCI2_CTL1 and PSIO0_CH1. |
| 37 | PC.3 | bidirectional | GPIO PC.3 multiplexed with EBI_AD3, QSPI0_SS, UART2_nRTS, I2C0_SMBAL, PWM1_CH2, USCI2_CTL0 and PSIO0_CH2. |
| 38 | PC.2 | bidirectional | GPIO PC.2 multiplexed with EBI_AD2, QSPI0_CLK, UART2_nCTS, I2C0_SMBSUS, PWM1_CH3, USCI2_CLK and PSIO0_CH3. |
| 39 | PC.1 | bidirectional | GPIO PC.1 multiplexed with EBI_AD1, QSPI0_MISO0, UART2_TXD, I2C0_SCL, PWM1_CH4, USCI2_DAT0 and ACMP0_O. |
| 40 | PC.0 | bidirectional | GPIO PC.0 multiplexed with EBI_AD0, QSPI0_MOSI0, UART2_RXD, I2C0_SDA, PWM1_CH5, USCI2_DAT1 and ACMP1_O. |
| 41 | PD.3 | bidirectional | GPIO PD.3 multiplexed with EBI_AD10, USCI0_CTL1, SPI0_SS, USCI1_CTL0 and UART0_TXD. |
| 42 | PD.2 | bidirectional | GPIO PD.2 multiplexed with EBI_AD11, USCI0_DAT1, SPI0_CLK and UART0_RXD. |
| 43 | PD.1 | bidirectional | GPIO PD.1 multiplexed with EBI_AD12, USCI0_DAT0 and SPI0_MISO. |
| 44 | PD.0 | bidirectional | GPIO PD.0 multiplexed with EBI_AD13, USCI0_CLK, SPI0_MOSI and TM2. |
| 45 | USB_VBUS | power_in | Power supply from USB host or HUB. |
| 46 | USB_D- | bidirectional | USB differential signal D-. |
| 47 | USB_D+ | bidirectional | USB differential signal D+. |
| 48 | USB_VDD33_CAP | passive | Internal power regulator output 3.3V decoupling pin. |
| 49 | VSS | power_in | Ground pin for digital circuit. |
| 50 | LDO_CAP | passive | LDO output pin; needs to be connected with a 1uF capacitor. |
| 51 | VDD | power_in | Power supply for I/O ports and LDO source for internal PLL and digital circuit. |
| 52 | PC.14 | bidirectional | GPIO PC.14 multiplexed with EBI_AD11, SPI0_I2SMCLK, USCI0_CTL0, QSPI0_CLK, USCI2_CLK and TM1. |
| 53 | PB.15 | bidirectional | GPIO PB.15 multiplexed with EADC0_CH15, EBI_AD12, SPI0_SS, USCI0_CTL1, UART0_nCTS, PSIO0_CH0, PWM1_CH0, TM0_EXT and PWM0_BRAKE1. |
| 54 | PB.14 | bidirectional | GPIO PB.14 multiplexed with EADC0_CH14, EBI_AD13, SPI0_CLK, USCI0_DAT1, UART0_nRTS, PSIO0_CH1, PWM1_CH1, TM1_EXT and CLKO. |
| 55 | PB.13 | bidirectional | GPIO PB.13 multiplexed with EADC0_CH13, ACMP0_P3, ACMP1_P3, EBI_AD14, SPI0_MISO, USCI0_DAT0, UART0_TXD, PSIO0_CH2, PWM1_CH2 and TM2_EXT. |
| 56 | PB.12 | bidirectional | GPIO PB.12 multiplexed with EADC0_CH12, ACMP0_P2, ACMP1_P2, EBI_AD15, SPI0_MOSI, USCI0_CLK, UART0_RXD, PSIO0_CH3, PWM1_CH3 and TM3_EXT. |
| 57 | AVDD | power_in | Power supply for internal analog circuit. |
| 58 | VREF | power_in | ADC reference voltage input; needs to be connected with a 1uF capacitor. |
| 59 | AVSS | power_in | Ground pin for analog circuit. |
| 60 | PB.11 | bidirectional | GPIO PB.11 multiplexed with EADC0_CH11, EBI_ADR16, UART0_nCTS, I2C1_SCL, SPI0_I2SMCLK and BPWM1_CH0. |
| 61 | PB.10 | bidirectional | GPIO PB.10 multiplexed with EADC0_CH10, EBI_ADR17, USCI1_CTL0, UART0_nRTS, I2C1_SDA and BPWM1_CH1. |
| 62 | PB.9 | bidirectional | GPIO PB.9 multiplexed with EADC0_CH9, EBI_ADR18, USCI1_CTL1, UART0_TXD, UART1_nCTS, I2C1_SMBAL and BPWM1_CH2. |
| 63 | PB.8 | bidirectional | GPIO PB.8 multiplexed with EADC0_CH8, EBI_ADR19, USCI1_CLK, UART0_RXD, UART1_nRTS, I2C1_SMBSUS and BPWM1_CH3. |
| 64 | PB.7 | bidirectional | GPIO PB.7 multiplexed with EADC0_CH7, EBI_nWRL, USCI1_DAT0, UART1_TXD, EBI_nCS0, BPWM1_CH4, PWM1_BRAKE0, PWM1_CH4, INT5 and ACMP0_O. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nuvoton Tech |
| Package | LQFP-64(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC power supply | VDD-VSS | -0.3 |  | 6.5 | V |  | 197 |
| VDDIO power supply | VDDIO-VSS | -0.3 |  | 6.5 | V |  | 197 |
| VBAT power supply | VBAT-VSS | -0.3 |  | 6.5 | V |  | 197 |
| Input voltage on any other pin | VIN | -0.3 |  | 6.5 | V | VSS-0.3 to 6.5 V | 197 |
| Maximum current into VDD | ΣIDD |  |  | 200 | mA |  | 198 |
| Maximum current out of VSS | ΣISS |  |  | 100 | mA |  | 198 |
| Maximum current sunk by an I/O pin | IIO |  |  | 20 | mA |  | 198 |
| Maximum current sourced by an I/O pin | IIO |  |  | 20 | mA |  | 198 |
| Maximum injected current by an I/O pin | IINJ(PIN) | -5 |  | 5 | mA |  | 198 |
| Maximum injected current by total I/O pins | ΣIINJ(PIN) | -25 |  | 25 | mA |  | 198 |
| Operating ambient temperature | TA | -40 |  | 105 | ℃ |  | 204 |
| Operating junction temperature | TJ | -40 |  | 125 | ℃ |  | 199 |
| Storage temperature | TST | -65 |  | 150 | ℃ |  | 199 |
| Thermal resistance junction-ambient, 64-pin LQFP(7x7 mm) | θJA |  | 58 |  | ℃/Watt | JESD51-2 | 199 |
| ESD human body model | VHBM | -6000 |  | 6000 | V |  | 201 |
| ESD charge device model | VCDM | -500 |  | 500 | V |  | 201 |
| Latch-up pin current | LU | -150 |  | 150 | mA | Class I | 201 |
| Operation voltage | VDD | 1.75 |  | 5.5 | V |  | 204 |
| VDDIO operation voltage | VDDIO | 1.65 |  | 5.5 | V |  | 204 |
| VBAT operation voltage | VBAT | 1.75 |  | 5.5 | V |  | 204 |
| Internal AHB clock frequency | fHCLK |  |  | 48 | MHz |  | 204 |
| ESR of CLDO output capacitor | RESR |  |  | 0.5 | Ω |  | 204 |
| Band-gap voltage | VBG | 795 | 815 | 840 | mV |  | 204 |
| LDO output voltage | VLDO |  | 1.5 |  | V |  | 204 |
| Inrush current on voltage regulator power-on | IRUSH |  | 60 | 150 | mA |  | 204 |
| Normal run current, peripherals disabled | IDD_RUN |  | 6.2 | 7.35 | mA | PL0, from Flash, all peripherals disable, HIRC/PLL/HXT, 48 MHz; typ TA=25 °C, max TA=105 °C | 208 |
| Normal run current, peripherals enabled | IDD_RUN |  | 17.5 | 20 | mA | PL0, from Flash, all peripherals enable, HIRC/PLL/HXT, 48 MHz; typ TA=25 °C, max TA=105 °C | 208 |
| Idle current, peripherals disabled | IDD_IDLE |  | 2.4 | 3.05 | mA | PL0, all peripherals disable, HIRC/PLL/HXT, 48 MHz; typ TA=25 °C, max TA=105 °C | 209 |
| Wakeup from IDLE mode | tWU_IDLE |  | 5 | 6 | cycles | 48 MHz HIRC | 212 |
| Wakeup from deep Power-down mode | tWU_DPD |  | 190 | 250 | µS |  | 212 |
| Wakeup from normal Power-down mode | tWU_NPD |  | 19 | 30 | µS |  | 212 |
| Wakeup from fast wake up Power-down mode | tWU_FWPD |  | 12 | 15 | µS |  | 212 |
| Input low voltage (Schmitt trigger) | VIL | 0 |  | 0.3 | V | max is 0.3*VDD | 213 |
| Input high voltage (Schmitt trigger) | VIH | 0.7 |  |  | V | min is 0.7*VDD, max VDD | 213 |
| Input leakage current | ILK | -1 |  | 1 | A | VSS < VIN < VDD, Open-drain or input only mode | 213 |
| Pull up resistor | RPU | 45 | 52 | 57 | kΩ |  | 213 |
| Pull down resistor | RPD | 45 | 52 | 57 | kΩ |  | 213 |
| Source current push-pull high level | ISR | -5 | -8 | -10.5 | mA | VDD = 4.5 V, VIN=(VDD-0.4) V | 214 |
| Sink current push-pull low level | ISK | 13 | 20 | 27 | mA | VDD = 4.5 V, VIN= 0.4 V | 214 |
| I/O pin capacitance | CIO |  | 5 |  | pF |  | 214 |
| Internal nRESET pull up resistor | RRST | 45 | 53 | 47 | kΩ |  | 215 |
| HIRC oscillator frequency | fHRC | 47.52 | 48 | 48.48 | MHz | TA = 25 °C, VDD = 3.3V | 216 |
| HIRC frequency drift over temperature and voltage |  | -2.8 |  | 2.8 | % | TA = -40C ~ +105 °C, VDD = 1.75 ~ 5.5V | 216 |
| MIRC oscillator frequency | FMRC | 3.951 | 4.032 | 4.112 | MHz | TA = 25 °C, VDD = 3.3V | 217 |
| MIRC frequency drift over temperature and voltage |  | -10 |  | 10 | % | TA = -40C ~ +105 °C, VDD = 1.75 ~ 5.5V | 217 |
| LIRC frequency drift over temperature and voltage |  | -15 |  | 15 | % | TA=-40~105°C, VDD=1.75V~5.5V, Without software calibration | 218 |
| POR reset voltage | VPOR | 1.4 | 1.5 | 1.65 | V |  | 230 |
| LVR reset voltage | VLVR | 1.55 | 1.6 | 1.7 | V |  | 230 |
| BOD brown-out detect voltage (falling edge) | VBOD | 2.9 | 3 | 3.1 | V | BODVL = 5 | 230 |
| ADC analog operating voltage | AVDD | 1.75 |  | 5.5 | V | VDD = AVDD | 232 |
| ADC integral non-linearity error | INL | -3 |  | 3 | LSB | VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 | 232 |
| ADC differential non-linearity error | DNL | -1 |  | 3 | LSB | VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 | 232 |
| ADC gain error | EG | -6 |  | 6 | LSB | VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 | 232 |
| ADC offset error | EO | -3 |  | 3 | LSB | VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 | 232 |
| ADC absolute error | EA | -1.5 |  | 6.5 | LSB | VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 | 232 |
| ADC sampling rate | FSPS | 250 |  | 730 | kSPS | FSPS = FADC / TCONV | 232 |
| Internal reference voltage | VREF_INT | 2.97 | 3.072 | 3.17 | V | AVDD >= 3.4 V | 239 |
| Temperature sensor offset voltage | VTEMP_OS | 690 | 720 | 750 | mV | TA = 0°C | 240 |
| Temperature sensor temperature coefficient | TC | -1.74 | -1.83 | -1.9 | mV/°C |  | 240 |
| Flash endurance | NENDUR | 20000 |  |  | cycles |  | 252 |
| Flash data retention | TRET | 10 |  |  | year | 20 kcycle, TJ = 125℃ | 252 |

## CAD (KiCad official)

- Symbol: `M252SE3AE`
- Footprint: `Package_QFP:LQFP-64_7x7mm_P0.4mm`
- 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
- 3D model files: `m252se3ae-etched.step` / `m252se3ae-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `m252se3ae.step` / `m252se3ae.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nuvoton Tech datasheet](docs/m252se3ae-datasheet.pdf) (263 pp, sha256 `5adaa62150d5740c`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/m252se3ae-datasheet.pdf)