component
M24M01-DFMN6TP
Public Made by Adomby adom
STMicroelectronics EEPROM, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownM24M01-DFMN6TP
STMicroelectronics · EEPROM · SO-8
M24M01-DFMN6TP from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DU | unconnected | Don't use: no signal should be applied on this pin, and if connected it must be connected to VSS. |
| 2 | E1 | input | Chip Enable input that sets device select code bit b2 and must be tied to VCC or VSS, reading as low when left floating. |
| 3 | E2 | input | Chip Enable input that sets device select code bit b3 and must be tied to VCC or VSS, reading as low when left floating. |
| 4 | VSS | power_in | Ground, the reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Serial data input/output with an open-drain output that needs an external pull-up resistor. |
| 6 | SCL | input | Serial clock input that strobes data into and out of SDA. |
| 7 | WC | input | Write Control input that disables writes to the whole memory array when driven high and enables them when driven low or left floating. |
| 8 | VCC | power_in | Supply voltage of 1.7 V to 5.5 V for the M24M01-DF, to be decoupled with about 10 nF to 100 nF close to the VCC/VSS pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 1.7 | 5.5 | V | voltage range F | 24 | |
| Ambient operating temperature | TA | -40 | 85 | °C | voltage range F | 24 | |
| Operating clock frequency | fC | 1 | MHz | voltage range F | 24 | ||
| Ambient operating temperature | -40 | 130 | °C | 23 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 23 | ||
| DC output current | IOL | 5 | mA | SDA = 0 | 23 | ||
| Input or output range | VIO | -0.5 | 6.5 | V | 23 | ||
| Supply voltage | VCC | -0.5 | 6.5 | V | 23 | ||
| Electrostatic pulse (Human Body model) | VESD | 4000 | V | 23 | |||
| Input leakage current (E1, E2, SCL, SDA) | ILI | -2 | 2 | µA | VIN = VSS or VCC, device in Standby mode | 27 | |
| Output leakage current | ILO | -2 | 2 | µA | SDA in Hi-Z, external voltage applied on SDA: VSS or VCC | 27 | |
| Supply current (Read) | ICC | 1 | mA | VCC = 1.7 V, fc = 400 kHz | 27 | ||
| Supply current (Read) | ICC | 1.5 | mA | VCC = 5.5 V, fc = 400 kHz | 27 | ||
| Supply current (Write) | ICC0 | 2 | mA | During tW; characterized only, not tested in production | 27 | ||
| Standby supply current | ICC1 | 3 | µA | Device not selected, VIN = VSS or VCC, VCC = 1.7 V | 27 | ||
| Standby supply current | ICC1 | 5 | µA | Device not selected, VIN = VSS or VCC, VCC = 5.5 V | 27 | ||
| Input low voltage (Ei, SCL, SDA, WC) minimum | VIL | -0.45 | V | 1.7 V ≤ VCC < 5.5 V | 27 | ||
| Input low voltage (Ei, SCL, SDA, WC) maximum | VIL | 0.25 | VCC | 1.7 V ≤ VCC < 2.5 V | 27 | ||
| Input low voltage (Ei, SCL, SDA, WC) maximum | VIL | 0.3 | VCC | 2.5 V ≤ VCC < 5.5 V | 27 | ||
| Input high voltage (Ei, SCL, SDA, WC) minimum | VIH | 0.75 | VCC | 1.7 V ≤ VCC < 2.5 V | 27 | ||
| Input high voltage (Ei, SCL, SDA, WC) minimum | VIH | 0.7 | VCC | 2.5 V ≤ VCC < 5.5 V | 27 | ||
| Output low voltage | VOL | 0.2 | V | IOL = 1.0 mA, VCC = 1.7 V | 27 | ||
| Output low voltage | VOL | 0.4 | V | IOL = 2.1 mA, VCC = 2.5 V | 27 | ||
| Input capacitance (SDA) | CIN | 8 | pF | Sampled only, not 100% tested | 24 | ||
| Input capacitance (other pins) | CIN | 6 | pF | Sampled only, not 100% tested | 24 | ||
| Input impedance (WC) | ZL | 30 | kΩ | VIN < 0.3 VCC | 24 | ||
| Input impedance (WC) | ZH | 400 | kΩ | VIN > 0.7 VCC | 24 | ||
| Write cycle endurance | Ncycle | 4e+06 | Write cycle | TA ≤ 25 °C, VCC(min) < VCC < VCC(max) | 25 | ||
| Write cycle endurance | Ncycle | 1.2e+06 | Write cycle | TA = 85 °C, VCC(min) < VCC < VCC(max) | 25 | ||
| Data retention | 200 | Year | TA = 55 °C | 25 | |||
| Clock frequency (400 kHz) | fC | 400 | kHz | 28 | |||
| Clock pulse width high (400 kHz) | tCHCL | 600 | ns | 28 | |||
| Clock pulse width low (400 kHz) | tCLCH | 1300 | ns | 28 | |||
| SDA (out) fall time (400 kHz) | tQL1QL2 | 20 | 300 | ns | Characterized only; min with CL = 10 pF | 28 | |
| Data in set up time (400 kHz) | tDXCH | 100 | ns | 28 | |||
| Data in hold time (400 kHz) | tCLDX | 0 | ns | 28 | |||
| Data out hold time (400 kHz) | tCLQX | 100 | ns | 28 | |||
| Clock low to next data valid (400 kHz) | tCLQV | 900 | ns | 28 | |||
| Start condition setup time (400 kHz) | tCHDL | 600 | ns | 28 | |||
| Start condition hold time (400 kHz) | tDLCL | 600 | ns | 28 | |||
| Stop condition set up time (400 kHz) | tCHDH | 600 | ns | 28 | |||
| Time between Stop and next Start (400 kHz) | tDHDL | 1300 | ns | 28 | |||
| WC set up time (400 kHz) | tWLDL | 0 | µs | Characterized only | 28 | ||
| WC hold time (400 kHz) | tDHWH | 1 | µs | Characterized only | 28 | ||
| Internal Write cycle duration (400 kHz) | tW | 5 | ms | 28 | |||
| Pulse width ignored (400 kHz) | tNS | 50 | ns | Input filter on SCL and SDA, single glitch; characterized only | 28 | ||
| Clock frequency (1 MHz) | fC | 0 | 1 | MHz | 29 | ||
| Clock pulse width high (1 MHz) | tCHCL | 300 | ns | 29 | |||
| Clock pulse width low (1 MHz) | tCLCH | 400 | ns | 29 | |||
| SDA (out) fall time (1 MHz) | tQL1QL2 | 120 | ns | 29 | |||
| Data in setup time (1 MHz) | tDXCX | 80 | ns | 29 | |||
| Clock low to next data valid (1 MHz) | tCLQV | 500 | ns | 29 | |||
| Start condition setup time (1 MHz) | tCHDL | 250 | ns | 29 | |||
| Start condition hold time (1 MHz) | tDLCL | 250 | ns | 29 | |||
| Stop condition setup time (1 MHz) | tCHDH | 250 | ns | 29 | |||
| Time between Stop and next Start (1 MHz) | tDHDL | 500 | ns | 29 | |||
| Write time (1 MHz) | tW | 5 | ms | 29 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | TLEAD Lead temperature during soldering see note (1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK® | 23 |
CAD (KiCad official)
- Symbol:
M24M01-DFMN6TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
m24m01-dfmn6tp-etched.step/m24m01-dfmn6tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);m24m01-dfmn6tp.step/m24m01-dfmn6tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (47 pp, sha256
2fcf2a055ea9b4cc, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).