component
M24C02-DRMN8TP
Public Made by Adomby adom
STMicroelectronics EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
M24C02-DRMN8TP
STMicroelectronics · EEPROM · SOP-8
M24C02-DRMN8TP from STMicroelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Chip enable input that sets bit b1 of the 7-bit device select code; it must be tied to VCC or VSS, and reads as low (0) when left floating. |
| 2 | E1 | input | Chip enable input that sets bit b2 of the 7-bit device select code; it must be tied to VCC or VSS, and reads as low (0) when left floating. |
| 3 | E2 | input | Chip enable input that sets bit b3 of the 7-bit device select code; it must be tied to VCC or VSS, and reads as low (0) when left floating. |
| 4 | VSS | power_in | Ground, the reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Serial data I/O, an open-drain output that needs a pull-up resistor to VCC; input high level is 0.7 VCC to 6.5 V and output low is 0.4 V max at 3 mA with VCC = 5.5 V. |
| 6 | SCL | input | Serial clock input that strobes data on SDA in and out; input high level is 0.7 VCC to 6.5 V. |
| 7 | WC | input | Write control: driving it high inhibits all write operations (data bytes are not acknowledged), while driving it low or leaving it floating enables writes; input high is 0.7 VCC to VCC + 0.6 V. |
| 8 | VCC | power_in | Supply voltage, specified from 1.7 V to 5.5 V with decoupling of 10 nF to 100 nF recommended close to the VCC/VSS pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
M24C02-DRMN8TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
m24c02-drmn8tp-etched.step/m24c02-drmn8tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);m24c02-drmn8tp.step/m24c02-drmn8tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (42 pp, sha256
ca15ee09e38f09bf, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# M24C02-DRMN8TP
**STMicroelectronics** · EEPROM · SOP-8
M24C02-DRMN8TP from STMicroelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Chip enable input that sets bit b1 of the 7-bit device select code; it must be tied to VCC or VSS, and reads as low (0) when left floating. |
| 2 | E1 | input | Chip enable input that sets bit b2 of the 7-bit device select code; it must be tied to VCC or VSS, and reads as low (0) when left floating. |
| 3 | E2 | input | Chip enable input that sets bit b3 of the 7-bit device select code; it must be tied to VCC or VSS, and reads as low (0) when left floating. |
| 4 | VSS | power_in | Ground, the reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Serial data I/O, an open-drain output that needs a pull-up resistor to VCC; input high level is 0.7 VCC to 6.5 V and output low is 0.4 V max at 3 mA with VCC = 5.5 V. |
| 6 | SCL | input | Serial clock input that strobes data on SDA in and out; input high level is 0.7 VCC to 6.5 V. |
| 7 | WC | input | Write control: driving it high inhibits all write operations (data bytes are not acknowledged), while driving it low or leaving it floating enables writes; input high is 0.7 VCC to VCC + 0.6 V. |
| 8 | VCC | power_in | Supply voltage, specified from 1.7 V to 5.5 V with decoupling of 10 nF to 100 nF recommended close to the VCC/VSS pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `M24C02-DRMN8TP`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `m24c02-drmn8tp-etched.step` / `m24c02-drmn8tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `m24c02-drmn8tp.step` / `m24c02-drmn8tp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589828390338256896) (42 pp, sha256 `ca15ee09e38f09bf`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/m24c02-drmn8tp-datasheet.pdf)