component
M24C01-RDW6TP
Public Made by Adomby adom
STMicroelectronics EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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M24C01-RDW6TP
STMicroelectronics · EEPROM · TSSOP-8
M24C01-RDW6TP from STMicroelectronics, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Chip Enable input that sets the least significant bit (b1) of the 7-bit device select code and must be tied to VCC or VSS, reading as low when left floating. |
| 2 | E1 | input | Chip Enable input that sets bit b2 of the 7-bit device select code and must be tied to VCC or VSS, reading as low when left floating. |
| 3 | E2 | input | Chip Enable input that sets bit b3 of the 7-bit device select code and must be tied to VCC or VSS, reading as low when left floating. |
| 4 | VSS | power_in | Ground, the reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Serial data input/output with an open-drain output that needs a pull-up resistor to VCC. |
| 6 | SCL | input | Serial clock input that strobes data in on SDA and clocks data out on SDA. |
| 7 | WC | input | Write Control input, active high: driving it high disables writes to the entire memory array, and driving it low or leaving it floating enables writes. |
| 8 | VCC | power_in | Supply voltage, 1.8 V to 5.5 V for the R range, to be decoupled with about 10 nF to 100 nF close to the VCC/VSS pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input leakage current (Ei, SCL, SDA) | ILI | -2 | 2 | µA | VIN = VSS or VCC, device in Standby mode | 25 | |
| Output leakage current | ILO | -2 | 2 | µA | SDA in Hi-Z, external voltage applied on SDA: VSS or VCC | 25 | |
| Supply current (Read) | ICC | 0.8 | mA | VCC = 1.8 V, fc = 400 kHz | 25 | ||
| Supply current (Write) | ICC0 | 0.5 | mA | During tW, VCC = 1.8 V ≤ VCC ≤ 2.5 V | 25 | ||
| Standby supply current | ICC1 | 1 | µA | Device not selected, VIN = VSS or VCC, VCC = 1.8 V | 25 | ||
| Input low voltage (SCL, SDA, WC) | VIL | -0.45 | V | 2.5 V ≤ VCC | 25 | ||
| Input low voltage (SCL, SDA, WC) | VIL | 0.3 | ×VCC | 2.5 V ≤ VCC | 25 | ||
| Input low voltage (SCL, SDA, WC) | VIL | 0.25 | ×VCC | VCC < 2.5 V | 25 | ||
| Input high voltage (SCL, SDA) | VIH | 0.75 | ×VCC | VCC < 2.5 V | 25 | ||
| Input high voltage (SCL, SDA) | VIH | 6.5 | V | VCC < 2.5 V | 25 | ||
| Input high voltage (WC) | VIH | 0.75 | ×VCC | VCC < 2.5 V | 25 | ||
| Output low voltage | VOL | 0.2 | V | IOL = 0.7 mA, VCC = 1.8 V | 25 | ||
| Input capacitance (SDA) | CIN | 8 | pF | 23 | |||
| Input capacitance (other pins) | CIN | 6 | pF | 23 | |||
| Input impedance (Ei, WC) | ZL | 15 | 70 | kΩ | VIN < 0.3 VCC | 23 | |
| Input impedance (Ei, WC) | ZH | 500 | kΩ | VIN > 0.7 VCC | 23 | ||
| Write cycle endurance | Ncycle | 4e+06 | Write cycle | TA ≤ 25 °C, VCC(min) < VCC < VCC(max) | 23 | ||
| Write cycle endurance | Ncycle | 1.2e+06 | Write cycle | TA = 85 °C, VCC(min) < VCC < VCC(max) | 23 | ||
| Data retention | 200 | Year | TA = 55 °C | 23 | |||
| Ambient operating temperature (recommended) | TA | -40 | 85 | °C | voltage range R | 22 | |
| Supply voltage (recommended) | VCC | 1.8 | 5.5 | V | voltage range R | 22 | |
| Operating clock frequency (recommended) | fC | 400 | kHz | voltage range R | 22 | ||
| Load capacitance | Cbus | 0 | 100 | pF | 22 | ||
| SCL input rise/fall time, SDA input fall time | 50 | ns | 22 | ||||
| Clock frequency (400 kHz Fast-mode) | fC | 400 | kHz | I2C Fast-mode, 400 kHz | 27 | ||
| Clock pulse width high | tCHCL | 600 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Clock pulse width low | tCLCH | 1300 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| SDA (out) fall time | tQL1QL2 | 20 | 300 | ns | CL = 10 pF | 27 | |
| Data in set up time | tDXCH | 100 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Data in hold time | tCLDX | 0 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Data out hold time | tCLQX | 100 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Clock low to next data valid (access time) | tCLQV | 900 | ns | Rbus × Cbus within Figure 11 values | 27 | ||
| Start condition setup time | tCHDL | 600 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Start condition hold time | tDLCL | 600 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Stop condition set up time | tCHDH | 600 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Time between Stop condition and next Start condition | tDHDL | 1300 | ns | I2C Fast-mode, 400 kHz | 27 | ||
| Write time | tW | 5 | ms | 27 | |||
| Pulse width ignored (input filter on SCL and SDA), single glitch | tNS | 100 | ns | 27 | |||
| Clock frequency (100 kHz Standard mode) | fC | 100 | kHz | I2C Standard mode, 100 kHz | 28 | ||
| Clock pulse width high | tCHCL | 4 | µs | I2C Standard mode, 100 kHz | 28 | ||
| Clock pulse width low | tCLCH | 4.7 | µs | I2C Standard mode, 100 kHz | 28 | ||
| Input signal rise time | tXH1XH2 | 1 | µs | I2C Standard mode, 100 kHz | 28 | ||
| Input signal fall time | tXL1XL2 | 300 | ns | I2C Standard mode, 100 kHz | 28 | ||
| SDA fall time | tQL1QL2 | 300 | ns | I2C Standard mode, 100 kHz; characterized only | 28 | ||
| Data in setup time | tDXCH | 250 | ns | I2C Standard mode, 100 kHz | 28 | ||
| Data out hold time | tCLQX | 200 | ns | I2C Standard mode, 100 kHz | 28 | ||
| Clock low to next data valid (access time) | tCLQV | 3450 | ns | Rbus × Cbus within Figure 11 values | 28 | ||
| Start condition setup time | tCHDL | 4.7 | µs | For a reStart condition, or following a Write cycle | 28 | ||
| Start condition hold time | tDLCL | 4 | µs | I2C Standard mode, 100 kHz | 28 | ||
| Stop condition setup time | tCHDH | 4 | µs | I2C Standard mode, 100 kHz | 28 | ||
| Time between Stop condition and next Start condition | tDHDL | 4.7 | µs | I2C Standard mode, 100 kHz | 28 | ||
| Write time | tW | 5 | ms | I2C Standard mode, 100 kHz | 28 | ||
| Pulse width ignored (input filter on SCL and SDA), single glitch | tNS | 100 | ns | I2C Standard mode, 100 kHz | 28 | ||
| Ambient operating temperature (absolute maximum) | 130 | °C | 21 | ||||
| Storage temperature | TSTG | -65 | 150 | °C | 21 | ||
| DC output current | IOL | 5 | mA | SDA = 0 | 21 | ||
| Input or output range | VIO | -0.5 | 6.5 | V | 21 | ||
| Supply voltage (absolute maximum) | VCC | -0.5 | 6.5 | V | 21 | ||
| Electrostatic pulse (Human Body model) | VESD | 3000 | V | Human Body model | 21 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Lead temperature during soldering see note(1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK2® | 21 |
CAD (KiCad official)
- Symbol:
M24C01-RDW6TP - Footprint:
Package_SO:TSSOP-8_4.4x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
m24c01-rdw6tp-etched.step/m24c01-rdw6tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);m24c01-rdw6tp.step/m24c01-rdw6tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (42 pp, sha256
943c0b9f52652f9b, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# M24C01-RDW6TP
**STMicroelectronics** · EEPROM · TSSOP-8
M24C01-RDW6TP from STMicroelectronics, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Chip Enable input that sets the least significant bit (b1) of the 7-bit device select code and must be tied to VCC or VSS, reading as low when left floating. |
| 2 | E1 | input | Chip Enable input that sets bit b2 of the 7-bit device select code and must be tied to VCC or VSS, reading as low when left floating. |
| 3 | E2 | input | Chip Enable input that sets bit b3 of the 7-bit device select code and must be tied to VCC or VSS, reading as low when left floating. |
| 4 | VSS | power_in | Ground, the reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Serial data input/output with an open-drain output that needs a pull-up resistor to VCC. |
| 6 | SCL | input | Serial clock input that strobes data in on SDA and clocks data out on SDA. |
| 7 | WC | input | Write Control input, active high: driving it high disables writes to the entire memory array, and driving it low or leaving it floating enables writes. |
| 8 | VCC | power_in | Supply voltage, 1.8 V to 5.5 V for the R range, to be decoupled with about 10 nF to 100 nF close to the VCC/VSS pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input leakage current (Ei, SCL, SDA) | ILI | -2 | | 2 | µA | VIN = VSS or VCC, device in Standby mode | 25 |
| Output leakage current | ILO | -2 | | 2 | µA | SDA in Hi-Z, external voltage applied on SDA: VSS or VCC | 25 |
| Supply current (Read) | ICC | | | 0.8 | mA | VCC = 1.8 V, fc = 400 kHz | 25 |
| Supply current (Write) | ICC0 | | | 0.5 | mA | During tW, VCC = 1.8 V ≤ VCC ≤ 2.5 V | 25 |
| Standby supply current | ICC1 | | | 1 | µA | Device not selected, VIN = VSS or VCC, VCC = 1.8 V | 25 |
| Input low voltage (SCL, SDA, WC) | VIL | -0.45 | | | V | 2.5 V ≤ VCC | 25 |
| Input low voltage (SCL, SDA, WC) | VIL | | | 0.3 | ×VCC | 2.5 V ≤ VCC | 25 |
| Input low voltage (SCL, SDA, WC) | VIL | | | 0.25 | ×VCC | VCC < 2.5 V | 25 |
| Input high voltage (SCL, SDA) | VIH | 0.75 | | | ×VCC | VCC < 2.5 V | 25 |
| Input high voltage (SCL, SDA) | VIH | | | 6.5 | V | VCC < 2.5 V | 25 |
| Input high voltage (WC) | VIH | 0.75 | | | ×VCC | VCC < 2.5 V | 25 |
| Output low voltage | VOL | | | 0.2 | V | IOL = 0.7 mA, VCC = 1.8 V | 25 |
| Input capacitance (SDA) | CIN | | | 8 | pF | | 23 |
| Input capacitance (other pins) | CIN | | | 6 | pF | | 23 |
| Input impedance (Ei, WC) | ZL | 15 | | 70 | kΩ | VIN < 0.3 VCC | 23 |
| Input impedance (Ei, WC) | ZH | 500 | | | kΩ | VIN > 0.7 VCC | 23 |
| Write cycle endurance | Ncycle | | | 4e+06 | Write cycle | TA ≤ 25 °C, VCC(min) < VCC < VCC(max) | 23 |
| Write cycle endurance | Ncycle | | | 1.2e+06 | Write cycle | TA = 85 °C, VCC(min) < VCC < VCC(max) | 23 |
| Data retention | | 200 | | | Year | TA = 55 °C | 23 |
| Ambient operating temperature (recommended) | TA | -40 | | 85 | °C | voltage range R | 22 |
| Supply voltage (recommended) | VCC | 1.8 | | 5.5 | V | voltage range R | 22 |
| Operating clock frequency (recommended) | fC | | | 400 | kHz | voltage range R | 22 |
| Load capacitance | Cbus | 0 | | 100 | pF | | 22 |
| SCL input rise/fall time, SDA input fall time | | | | 50 | ns | | 22 |
| Clock frequency (400 kHz Fast-mode) | fC | | | 400 | kHz | I2C Fast-mode, 400 kHz | 27 |
| Clock pulse width high | tCHCL | 600 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Clock pulse width low | tCLCH | 1300 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| SDA (out) fall time | tQL1QL2 | 20 | | 300 | ns | CL = 10 pF | 27 |
| Data in set up time | tDXCH | 100 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Data in hold time | tCLDX | 0 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Data out hold time | tCLQX | 100 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Clock low to next data valid (access time) | tCLQV | | | 900 | ns | Rbus × Cbus within Figure 11 values | 27 |
| Start condition setup time | tCHDL | 600 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Start condition hold time | tDLCL | 600 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Stop condition set up time | tCHDH | 600 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Time between Stop condition and next Start condition | tDHDL | 1300 | | | ns | I2C Fast-mode, 400 kHz | 27 |
| Write time | tW | | | 5 | ms | | 27 |
| Pulse width ignored (input filter on SCL and SDA), single glitch | tNS | | | 100 | ns | | 27 |
| Clock frequency (100 kHz Standard mode) | fC | | | 100 | kHz | I2C Standard mode, 100 kHz | 28 |
| Clock pulse width high | tCHCL | 4 | | | µs | I2C Standard mode, 100 kHz | 28 |
| Clock pulse width low | tCLCH | 4.7 | | | µs | I2C Standard mode, 100 kHz | 28 |
| Input signal rise time | tXH1XH2 | | | 1 | µs | I2C Standard mode, 100 kHz | 28 |
| Input signal fall time | tXL1XL2 | | | 300 | ns | I2C Standard mode, 100 kHz | 28 |
| SDA fall time | tQL1QL2 | | | 300 | ns | I2C Standard mode, 100 kHz; characterized only | 28 |
| Data in setup time | tDXCH | 250 | | | ns | I2C Standard mode, 100 kHz | 28 |
| Data out hold time | tCLQX | 200 | | | ns | I2C Standard mode, 100 kHz | 28 |
| Clock low to next data valid (access time) | tCLQV | | | 3450 | ns | Rbus × Cbus within Figure 11 values | 28 |
| Start condition setup time | tCHDL | 4.7 | | | µs | For a reStart condition, or following a Write cycle | 28 |
| Start condition hold time | tDLCL | 4 | | | µs | I2C Standard mode, 100 kHz | 28 |
| Stop condition setup time | tCHDH | 4 | | | µs | I2C Standard mode, 100 kHz | 28 |
| Time between Stop condition and next Start condition | tDHDL | 4.7 | | | µs | I2C Standard mode, 100 kHz | 28 |
| Write time | tW | | | 5 | ms | I2C Standard mode, 100 kHz | 28 |
| Pulse width ignored (input filter on SCL and SDA), single glitch | tNS | | | 100 | ns | I2C Standard mode, 100 kHz | 28 |
| Ambient operating temperature (absolute maximum) | | | | 130 | °C | | 21 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 21 |
| DC output current | IOL | | | 5 | mA | SDA = 0 | 21 |
| Input or output range | VIO | -0.5 | | 6.5 | V | | 21 |
| Supply voltage (absolute maximum) | VCC | -0.5 | | 6.5 | V | | 21 |
| Electrostatic pulse (Human Body model) | VESD | | | 3000 | V | Human Body model | 21 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | Lead temperature during soldering see note(1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK2® | 21 |
## CAD (KiCad official)
- Symbol: `M24C01-RDW6TP`
- Footprint: `Package_SO:TSSOP-8_4.4x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `m24c01-rdw6tp-etched.step` / `m24c01-rdw6tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `m24c01-rdw6tp.step` / `m24c01-rdw6tp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/m24c01-rdw6tp.pdf) (42 pp, sha256 `943c0b9f52652f9b`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/m24c01-rdw6tp-datasheet.pdf)