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m2354sjfae

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Nuvoton Tech Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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M2354SJFAE

Nuvoton Tech · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(7x7)

M2354SJFAE from Nuvoton Tech, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB.6 bidirectional GPIO PB.6 with ADC input EADC0_CH6 and alternates including EBI_nWRH, USCI1_DAT1, UART1_RXD, EBI_nCS1, BPWM1_CH5, EPWM1_BRAKE1, EPWM1_CH5, INT4, USB_VBUS_EN and ACMP1_O.
2 PB.5 bidirectional GPIO PB.5 with ADC input EADC0_CH5 and alternates including ACMP1_N, EBI_ADR0, SD0_DAT3, SPI1_MISO, I2C0_SCL, UART5_TXD, EPWM0_CH0, UART2_TXD, TM0 and INT0.
3 PB.4 bidirectional GPIO PB.4 with ADC input EADC0_CH4 and alternates including ACMP1_P1, EBI_ADR1, SD0_DAT2, SPI1_MOSI, I2C0_SDA, UART5_RXD, EPWM0_CH1, UART2_RXD, TM1 and INT1.
4 PB.3 bidirectional GPIO PB.3 with ADC input EADC0_CH3 and alternates including ACMP0_N, EBI_ADR2, SD0_DAT1, SPI1_CLK, UART1_TXD, UART5_nRTS, SC0_RST, I2C1_SCL, EPWM0_CH2, TM4, TM2 and INT2.
5 PB.2 bidirectional GPIO PB.2 with ADC input EADC0_CH2 and alternates including ACMP0_P1, EBI_ADR3, SD0_DAT0, SPI1_SS, UART1_RXD, UART5_nCTS, SC0_PWR, I2S0_DO, EPWM0_CH3, I2C1_SDA, TM5, TM3 and INT3.
6 PB.1 bidirectional GPIO PB.1 with ADC input EADC0_CH1 and alternates including EBI_ADR8, SD0_CLK, SPI1_I2SMCLK, SPI3_I2SMCLK, UART2_TXD, USCI1_CLK, I2C1_SCL, I2S0_LRCK, EPWM0_CH4, EPWM1_CH4, EPWM0_BRAKE0 and QSPI0_MISO1.
7 PB.0 bidirectional GPIO PB.0 with ADC input EADC0_CH0 and alternates including EBI_ADR9, SD0_CMD, SPI2_I2SMCLK, UART2_RXD, SPI0_I2SMCLK, I2C1_SDA, EPWM0_CH5, EPWM1_CH5, EPWM0_BRAKE1 and QSPI0_MOSI1.
8 PA.11 bidirectional GPIO PA.11 with ACMP0_P0, EBI_nRD, SC2_PWR, SPI2_SS, USCI0_CLK, I2C2_SCL, BPWM0_CH0, EPWM0_SYNC_OUT, TM0_EXT and DAC1_ST alternate functions.
9 PA.10 bidirectional GPIO PA.10 with ACMP1_P0, EBI_nWR, SC2_RST, SPI2_CLK, USCI0_DAT0, I2C2_SDA, BPWM0_CH1, QEI1_INDEX, ECAP0_IC0, TM1_EXT and DAC0_ST alternate functions.
10 PA.9 bidirectional GPIO PA.9 with EBI_MCLK, SC2_DAT, SPI2_MISO, USCI0_DAT1, UART1_TXD, BPWM0_CH2, QEI1_A, ECAP0_IC1, TM4_EXT and TM2_EXT alternate functions.
11 PA.8 bidirectional GPIO PA.8 with EBI_ALE, SC2_CLK, SPI2_MOSI, USCI0_CTL1, UART1_RXD, BPWM0_CH3, QEI1_B, ECAP0_IC2, TM5_EXT, TM3_EXT and INT4 alternate functions.
12 PF.6 bidirectional GPIO PF.6 with EBI_ADR19, SC0_CLK, I2S0_LRCK, SPI0_MOSI, UART4_RXD, EBI_nCS0, SPI3_I2SMCLK and TAMPER0 tamper detector loop alternate functions.
13 VBAT power_in VBAT power domain supply pin, shown as the VBAT power domain in the pin diagram.
14 PF.5 bidirectional GPIO PF.5 with UART2_RXD, UART2_nCTS, EPWM0_CH0, BPWM0_CH4, EPWM0_SYNC_OUT, X32_IN (32.768 kHz crystal input) and EADC0_ST alternate functions.
15 PF.4 bidirectional GPIO PF.4 with UART2_TXD, UART2_nRTS, EPWM0_CH1, BPWM0_CH5 and X32_OUT (32.768 kHz crystal output) alternate functions.
16 PF.3 bidirectional GPIO PF.3 with EBI_nCS0, UART0_TXD, I2C0_SCL, XT1_IN (4~24 MHz crystal input), and BPWM1_CH0 alternate functions.
17 PF.2 bidirectional GPIO PF.2 with EBI_nCS1, UART0_RXD, I2C0_SDA, QSPI0_CLK, XT1_OUT (4~24 MHz crystal output) and BPWM1_CH1 alternate functions.
18 PC.7 bidirectional GPIO PC.7 with EBI_AD9, SPI1_MISO, UART4_TXD, SC2_PWR, UART0_nCTS, I2C1_SMBAL, EPWM1_CH2, BPWM1_CH0, LCD_SEG10, TM0 and INT3 alternate functions.
19 PC.6 bidirectional GPIO PC.6 with EBI_AD8, SPI1_MOSI, UART4_RXD, SC2_RST, UART0_nRTS, I2C1_SMBSUS, EPWM1_CH3, BPWM1_CH1, LCD_SEG9, TM1 and INT2 alternate functions.
20 PA.7 bidirectional GPIO PA.7 with EBI_AD7, SPI1_CLK, SC2_DAT, UART0_TXD, I2C1_SCL, LCD_SEG8, TM4, EPWM1_CH4, BPWM1_CH2, ACMP0_WLAT, TM2 and INT1 alternate functions.
21 PA.6 bidirectional GPIO PA.6 with EBI_AD6, SPI1_SS, SC2_CLK, UART0_RXD, I2C1_SDA, LCD_SEG7, TM5, EPWM1_CH5, BPWM1_CH3, ACMP1_WLAT, TM3 and INT0 alternate functions.
22 VSS power_in Ground pin (VSS) shown in the LQFP64 pin diagram.
23 VDD power_in Core supply pin (VDD) shown in the LQFP64 pin diagram.
24 LDO_CAP passive LDO_CAP pin for the internal CPU core LDO output capacitor connection, as shown in the LQFP64 pin diagram.
25 PA.5 bidirectional GPIO PA.5 with QSPI0_MISO1, SPI1_I2SMCLK, LCD_SEG6, SC2_nCD, UART0_nCTS, UART5_TXD, I2C0_SCL, CAN0_TXD, UART0_TXD, BPWM0_CH5, EPWM0_CH0 and QEI0_INDEX alternate functions.
26 PA.4 bidirectional GPIO PA.4 with QSPI0_MOSI1, SPI0_I2SMCLK, LCD_SEG5, SC0_nCD, UART0_nRTS, UART5_RXD, I2C0_SDA, CAN0_RXD, UART0_RXD, BPWM0_CH4, EPWM0_CH1 and QEI0_A alternate functions.
27 PA.3 bidirectional GPIO PA.3 with QSPI0_SS, SPI0_SS, LCD_SEG4, SC0_PWR, UART4_TXD, UART1_TXD, I2C1_SCL, I2C0_SMBAL, BPWM0_CH3, EPWM0_CH2, QEI0_B and EPWM1_BRAKE1 alternate functions.
28 PA.2 bidirectional GPIO PA.2 with QSPI0_CLK, SPI0_CLK, LCD_SEG3, SC0_RST, UART4_RXD, UART1_RXD, I2C1_SDA, I2C0_SMBSUS, BPWM0_CH2 and EPWM0_CH3 alternate functions.
29 PA.1 bidirectional GPIO PA.1 with QSPI0_MISO0, SPI0_MISO, LCD_COM7/SEG13, SC0_DAT, UART0_TXD, UART1_nCTS, I2C2_SCL, BPWM0_CH1, EPWM0_CH4 and DAC1_ST alternate functions.
30 PA.0 bidirectional GPIO PA.0 with QSPI0_MOSI0, SPI0_MOSI, LCD_COM6/SEG14, SC0_CLK, UART0_RXD, UART1_nRTS, I2C2_SDA, BPWM0_CH0, EPWM0_CH5 and DAC0_ST alternate functions.
31 VDDIO power_in VDDIO I/O power supply pin for the VDDIO power domain shown in the pin diagram.
32 nRESET input Active-low external reset input (nRESET) shown in the pin diagram.
33 PF.0 bidirectional GPIO PF.0 with UART1_TXD, I2C1_SCL, UART0_TXD, BPWM1_CH0 and ICE_DAT serial wired debugger data alternate functions; the datasheet recommends a 100 kΩ pull-up on ICE_DAT.
34 PF.1 bidirectional GPIO PF.1 with UART1_RXD, I2C1_SDA, UART0_RXD, BPWM1_CH1 and ICE_CLK serial wired debugger clock alternate functions; the datasheet recommends a 100 kΩ pull-up on ICE_CLK.
35 PC.5 bidirectional GPIO PC.5 with EBI_AD5, QSPI0_MISO1, UART2_TXD, I2C1_SCL, CAN0_TXD, UART4_TXD, EPWM1_CH0, LCD_SEG15 and LCD_COM5 alternate functions.
36 PC.4 bidirectional GPIO PC.4 with EBI_AD4, QSPI0_MOSI1, SC1_nCD, I2S0_BCLK, SPI1_I2SMCLK, UART2_RXD, I2C1_SDA, CAN0_RXD, UART4_RXD, EPWM1_CH1, LCD_SEG16 and LCD_COM4 alternate functions.
37 PC.3 bidirectional GPIO PC.3 with EBI_AD3, QSPI0_SS, SC1_PWR, I2S0_MCLK, SPI1_MISO, UART2_nRTS, I2C0_SMBAL, UART3_TXD, EPWM1_CH2 and LCD_COM3 alternate functions.
38 PC.2 bidirectional GPIO PC.2 with EBI_AD2, QSPI0_CLK, SC1_RST, I2S0_DI, SPI1_MOSI, UART2_nCTS, I2C0_SMBSUS, UART3_RXD, EPWM1_CH3 and LCD_COM2 alternate functions.
39 PC.1 bidirectional GPIO PC.1 with EBI_AD1, QSPI0_MISO0, SC1_DAT, I2S0_DO, SPI1_CLK, UART2_TXD, I2C0_SCL, EPWM1_CH4, LCD_COM1, ACMP0_O and EADC0_ST alternate functions.
40 PC.0 bidirectional GPIO PC.0 with EBI_AD0, QSPI0_MOSI0, SC1_CLK, I2S0_LRCK, SPI1_SS, UART2_RXD, I2C0_SDA, EPWM1_CH5, LCD_COM0 and ACMP1_O alternate functions.
41 PD.3 bidirectional GPIO PD.3 with EBI_AD10, USCI0_CTL1, SPI0_SS, UART3_nRTS, USCI1_CTL0, SC2_PWR, SC1_nCD, UART0_TXD and LCD_SEG2 alternate functions.
42 PD.2 bidirectional GPIO PD.2 with EBI_AD11, USCI0_DAT1, SPI0_CLK, UART3_nCTS, SC2_RST, UART0_RXD and LCD_SEG1 alternate functions.
43 PD.1 bidirectional GPIO PD.1 with EBI_AD12, USCI0_DAT0, SPI0_MISO, UART3_TXD, I2C2_SCL, SC2_DAT and LCD_SEG0 alternate functions.
44 VLCD power_in LCD power pin (VLCD) shown in the LQFP64 pin diagram.
45 PA.12 bidirectional GPIO PA.12 with I2S0_BCLK, UART4_TXD, I2C1_SCL, SPI2_SS, CAN0_TXD, SC2_PWR, BPWM1_CH2, QEI1_INDEX and USB_VBUS alternate functions.
46 PA.13 bidirectional GPIO PA.13 with I2S0_MCLK, UART4_RXD, I2C1_SDA, SPI2_CLK, CAN0_RXD, SC2_RST, BPWM1_CH3, QEI1_A and USB_D- alternate functions.
47 PA.14 bidirectional GPIO PA.14 with I2S0_DI, UART0_TXD, SPI2_MISO, I2C2_SCL, SC2_DAT, BPWM1_CH4, QEI1_B and USB_D+ alternate functions.
48 PA.15 bidirectional GPIO PA.15 with I2S0_DO, UART0_RXD, SPI2_MOSI, I2C2_SDA, SC2_CLK, BPWM1_CH5, EPWM0_SYNC_IN and USB_OTG_ID alternate functions.
49 VSS power_in Ground pin (VSS) shown in the LQFP64 pin diagram.
50 Vsw passive Vsw switching node pin for the DC-to-DC converter, as shown in the LQFP64 pin diagram.
51 VDD power_in Core supply pin (VDD) shown in the LQFP64 pin diagram.
52 LDO_CAP passive LDO_CAP pin for the internal CPU core LDO output capacitor connection, as shown in the LQFP64 pin diagram.
53 PB.15 bidirectional GPIO PB.15 with ADC input EADC0_CH15 and alternates including EBI_AD12, SC1_PWR, SPI0_SS, USCI0_CTL1, UART0_nCTS, UART3_TXD, I2C2_SMBAL, EPWM1_CH0, TM0_EXT and USB_VBUS_EN.
54 PB.14 bidirectional GPIO PB.14 with ADC input EADC0_CH14 and alternates including EBI_AD13, SC1_RST, SPI0_CLK, USCI0_DAT1, UART0_nRTS, UART3_RXD, I2C2_SMBSUS, EPWM0_BRAKE1, EPWM1_CH1, TM1_EXT, CLKO and USB_VBUS_ST.
55 PB.13 bidirectional GPIO PB.13 with ADC input EADC0_CH13 and alternates including DAC1_OUT, ACMP0_P3, ACMP1_P3, EBI_AD14, SC1_DAT, SPI0_MISO, USCI0_DAT0, UART0_TXD, UART3_nRTS, I2C2_SCL, EPWM1_CH2, TM2_EXT and TM4_EXT.
56 PB.12 bidirectional GPIO PB.12 with ADC input EADC0_CH12 and alternates including DAC0_OUT, ACMP0_P2, ACMP1_P2, EBI_AD15, SC1_CLK, SPI0_MOSI, USCI0_CLK, UART0_RXD, UART3_nCTS, I2C2_SDA, SD0_nCD, EPWM1_CH3, TM3_EXT and TM5_EXT.
57 AVDD power_in Analog supply pin (AVDD) shown in the LQFP64 pin diagram.
58 VREF power_in VREF analog reference voltage pin shown in the LQFP64 pin diagram.
59 AVSS power_in Analog ground pin (AVSS) shown in the LQFP64 pin diagram.
60 PB.11 bidirectional GPIO PB.11 with ADC input EADC0_CH11 and alternates including EBI_ADR16, UART0_nCTS, UART4_TXD, I2C1_SCL, CAN0_TXD, SPI0_I2SMCLK, BPWM1_CH0 and SPI3_CLK.
61 PB.10 bidirectional GPIO PB.10 with ADC input EADC0_CH10 and alternates including EBI_ADR17, USCI1_CTL0, UART0_nRTS, UART4_RXD, I2C1_SDA, CAN0_RXD, BPWM1_CH1 and SPI3_SS.
62 PB.9 bidirectional GPIO PB.9 with ADC input EADC0_CH9 and alternates including EBI_ADR18, USCI1_CTL1, UART0_TXD, UART1_nCTS, I2C1_SMBAL, I2C0_SCL, BPWM1_CH2, SPI3_MISO and INT7.
63 PB.8 bidirectional GPIO PB.8 with ADC input EADC0_CH8 and alternates including EBI_ADR19, USCI1_CLK, UART0_RXD, UART1_nRTS, I2C1_SMBSUS, I2C0_SDA, BPWM1_CH3, SPI3_MOSI and INT6.
64 PB.7 bidirectional GPIO PB.7 with ADC input EADC0_CH7 and alternates including EBI_nWRL, USCI1_DAT0, UART1_TXD, EBI_nCS0, BPWM1_CH4, EPWM1_BRAKE0, EPWM1_CH4, INT5, USB_VBUS_ST and ACMP0_O.

Key specifications

Parameter Value
Manufacturer Nuvoton Tech
Package LQFP-64(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC power supply VDD to VSS VDD-VSS -0.3 4 V 174
VDDIO power supply to VSS VDDIO-VSS -0.3 4 V 174
VBAT power supply to VSS VBAT-VSS -0.3 4 V 174
Maximum current into VDD ΣIDD 200 mA 174
Maximum current into VDDIO IDDIO 100 mA 174
Maximum current into VBAT IBAT 100 mA 174
Maximum current out of VSS ΣISS 100 mA 174
Maximum current sunk by an I/O pin IIO 20 mA 174
Maximum current sourced by an I/O pin IIO 20 mA 174
Maximum current sunk by total I/O pins 100 mA 174
Maximum current sourced by total I/O pins 100 mA 174
Maximum injected current by an I/O pin IINJ(PIN) -5 5 mA 174
Maximum injected current by total I/O pins ΣIINJ(PIN) -25 25 mA 174
Operating ambient temperature TA -40 105 ℃ 175
Operating junction temperature TJ -40 125 ℃ 175
Storage temperature TST -65 150 ℃ 175
Thermal resistance junction-ambient θJA 58 ℃/Watt 64-pin LQFP(7x7 mm) 175
Operating temperature TA -40 105 ℃ 178
Internal AHB clock frequency fHCLK 96 MHz 178
Operation voltage VDD 1.7 3.6 V 178
VDDIO operation voltage VDDIO 1.7 3.6 V 178
VBAT operation voltage VBAT 1.7 3.6 V 178
Analog reference voltage VREF 1.6 3.6 V 178
LDO output voltage (PL0) VLDO 1.134 1.26 1.386 V 178
LDO output voltage (PL3) VLDO 0.81 0.9 0.99 V 178
ESR of CLDO output capacitor RESR 0.5 Ω 178
LDO DC power supply VDD 1.7 3.6 V 205
LDO output voltage turbo mode VLDO 1.134 1.26 1.386 V Turbo mode 205
LDO maximum output current IOUT_MAX 50 mA VIN>1.7V 205
LDO operating temperature TA -40 125 ℃ 205
DC-DC input voltage range VIN 1.7 3.6 V 205
DC-DC maximum DC output current IOUT_MAX 50 mA VIN>1.7V 205
DC-DC quiescent current IQ_DCDC 4 6 uA No load, normal mode, only buck regulator 205
DC-DC line regulation VLINE -5 5 % IOUT=30mA, VIN=1.7V to 3.6V 205
DC-DC load regulation VLOAD -5 5 % IOUT=0.2mA to 30mA 206
DC-DC power efficiency PEFF 80 % IOUT= 2~30mA, LOUT = 4.7uH, DCR ≤ 180mΩ 206
LVR supply voltage AVDD 1.45 3.6 V 206
LVR threshold voltage VLVR 1.45 1.5 1.65 V 206
LVR operating current ILVR 0.3 0.6 uA AVDD = 3.6V (BOD_EN = 0) 206
Power-on reset voltage VPOR 1.38 1.46 1.54 V 206
Minimum time VDD stays at VPOR tPOR 10 us 206
BOD response time TBOD_RE 0.03 ms Sampled by LIRC 206
LVR response time TLVR_RE 20 us 206
12 MHz HIRC operating voltage VDD 1.7 3 3.6 V 196
12 MHz HIRC oscillator frequency fHRC 12 MHz 196
12 MHz HIRC frequency drift at 25 °C -0.25 0.25 % TA = 25 °C, VDD = 3.3 V 196
12 MHz HIRC frequency drift over temperature and voltage -4 4 % TA = -40C ~ +105 °C, VDD = 1.7 ~ 3.6V 196
12 MHz HIRC operating current IHRC 50 70 µA 196
12 MHz HIRC stable time TS 20 µs TA = -40C ~ +105 °C, VDD = 1.7 ~ 3.6V 196
32 kHz LIRC oscillator frequency FLRC 32 kHz 197
32 kHz LIRC frequency drift at 25 °C -0.4 0.4 % TA = 25 °C, VDD = 3.3 V 197
32 kHz LIRC frequency drift over temperature and voltage -15 15 % TA=-40105°C, VDD=1.7V3.6V 197
32 kHz LIRC operating current ILRC 0.6 0.8 µA VDD = 3.3V 197
32 kHz LIRC stable time TS 500 µs TA=-40105°C, VDD=1.7V3.6V 197
4 MHz MIRC oscillator frequency FLRC 4 MHz 197
4 MHz MIRC frequency drift at 25 °C -0.25 0.25 % TA = 25 °C, VDD = 3.3 V 198
4 MHz MIRC frequency drift over temperature and voltage -4 4 % TA=-40105°C, VDD=1.7V3.6V 198
4 MHz MIRC operating current ILRC 70 85 µA VDD = 3.3V 198
4 MHz MIRC stable time TS 20 µs TA=-40105°C, VDD=1.7V3.6V 198
HXT oscillator frequency fHXT 4 24 MHz 198
HXT temperature range THXT -40 105 C 198
HXT internal feedback resistor Rf 1000 kΩ 198
HXT duty cycle DuHXT 45 50 55 % 198
LXT operation voltage VDD 1.7 3.6 V 201
LXT temperature range TLXT -40 105 C 201
LXT stable time TsLXT 2000 ms 201
LXT duty cycle DuLXT 30 50 70 % 201
PLL input clock fPLL_in 4 24 MHz 203
PLL multiplier output clock fPLL_OUT 24 200 MHz 203
PLL voltage controlled oscillator fPLL_VCO 96 200 MHz 203
PLL locking time TL 100 µs 203
TTL input low voltage VIL1 0.8 V VDD = VDDIO = 3.6 V 193
TTL input high voltage VIH1 2 V VDD = VDDIO = 3.6V 193
TTL input low voltage VIL1 0.7 V VDD = VDDIO = 1.7 V 193
TTL input high voltage VIH1 1 V VDD = VDDIO = 1.7V 193
Schmitt input hysteresis voltage VHY 0.75 V VDD =3.6V 193
Input leakage current ILK -1 1 A VDD = VDDIO = 3.6V, 0 < VIN < VDD, Open-drain or input only mode 193
Input pull-up resistor RPU 52 KΩ VDD = VDDIO = 3.3V 193
Input pull-up resistor RPU 53 KΩ VDD = VDDIO = 1.8V 193
Input pull-down resistor RPD 52 KΩ VDD = VDDIO = 3.3V 193
Input pull-down resistor RPD 53 KΩ VDD = VDDIO = 1.8V 193
Internal nRESET pull-up resistor RRST 53.4 54 54.51 KΩ 194
nRESET input filtered time tFR1 32 uS VDD = 3.3V 194
SPI master data setup time tDS 0 ns SPI Master Mode (VDD = 3.0~3.6 V, 30 PF loading Capacitor) 217
SPI master data hold time tDH 10 ns SPI Master Mode (VDD = 3.0~3.6 V, 30 PF loading Capacitor) 217
SPI master data output valid time tV 0 15 ns SPI Master Mode (VDD = 3.0~3.6 V, 30 PF loading Capacitor) 217
I2C SCL low period tLOW 4.7 µs Standard Mode 221
I2C SCL low period tLOW 1.2 µs Fast Mode 221
I2C SCL high period tHIGH 4 µs Standard Mode 221
I2C SCL high period tHIGH 0.6 µs Fast Mode 221
USB full speed transceiver operating voltage VBUS 3 3.3 3.6 V 223
USB input high (driven) VIH 2 V 223
USB input low VIL 0.8 V 223
USB output low (driven) VOL 0 0.3 V 223
USB output high (driven) VOH 2.8 3.6 V 223
USB pull-down resistor RPD 14.25 24.8 kΩ 223
USB pull-up resistor RPU 1.425 3.09 kΩ 224
USB termination voltage for upstream port pull-up VTRM 3 3.6 V 224
USB driver output resistance ZDRV 10 Ω Steady state drive 224
USB transceiver capacitance CIN 26 pF Pin to GND 224
LCD controller supply voltage VDD 1.6 3.6 V 215
LCD controller operating temperature TA -20 85 ℃ 215

CAD (KiCad official)

  • Symbol: M2354SJFAE
  • Footprint: Package_QFP:LQFP-64_7x7mm_P0.4mm
  • 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
  • 3D model files: m2354sjfae-etched.step / m2354sjfae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m2354sjfae.step / m2354sjfae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nuvoton Tech datasheet (234 pp, sha256 5991424e03b884c2, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF