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M0516LDN

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Nuvoton Tech Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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M0516LDN

Nuvoton Tech · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

M0516LDN from Nuvoton Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.5 bidirectional Port 1 bit 5 general-purpose I/O (quasi-bidirectional, push-pull, open-drain, or input mode), also SPI0 MOSI_0, ADC input AIN5, and comparator 0 positive input ACMP0_P.
2 P1.6 bidirectional Port 1 bit 6 general-purpose I/O (quasi-bidirectional, push-pull, open-drain, or input mode), also SPI0 MISO_0, ADC input AIN6, and comparator 2 negative input ACMP2_N.
3 P1.7 bidirectional Port 1 bit 7 general-purpose I/O (quasi-bidirectional, push-pull, open-drain, or input mode), also SPI0 SPICLK0, ADC input AIN7, and comparator 2 positive input ACMP2_P.
4 nRST input Active-low Schmitt-trigger reset input with internal pull-up (40-150 kΩ); an external capacitor to ground gives power-on reset.
5 P3.0 bidirectional Port 3 bit 0 general-purpose I/O, also UART0 RXD and comparator 1 negative input ACMP1_N.
6 AVSS power_in Analog ground for the analog circuits (SAR ADC, comparators, references); must be tied to the common ground.
7 P3.1 bidirectional Port 3 bit 1 general-purpose I/O, also UART0 TXD and comparator 1 positive input ACMP1_P.
8 P3.2 bidirectional Port 3 bit 2 general-purpose I/O, also external interrupt nINT0, ADC external trigger STADC, and Timer0 external capture/reset T0EX.
9 P3.3 bidirectional Port 3 bit 3 general-purpose I/O, also external interrupt nINT1, EBI clock MCLK, and Timer1 external capture/reset T1EX.
10 P3.4 bidirectional Port 3 bit 4 general-purpose I/O (open-drain for I2C use), also Timer0 external event counter/toggle output T0 and I2C0 SDA.
11 P3.5 bidirectional Port 3 bit 5 general-purpose I/O (open-drain for I2C use), also Timer1 event counter/toggle output T1, I2C0 SCL, and clock monitor output CKO.
12 P4.3 bidirectional Port 4 bit 3 general-purpose I/O, also PWM channel 3 output PWM3.
13 P3.6 bidirectional Port 3 bit 6 general-purpose I/O, also EBI write strobe nWR, clock output CKO, and comparator 0 output ACMP0_O.
14 P3.7 bidirectional Port 3 bit 7 general-purpose I/O, also EBI read strobe nRD.
15 XTAL2 output External 4-24 MHz high-speed crystal oscillator output pin.
16 XTAL1 input External 4-24 MHz high-speed crystal oscillator input pin (CMOS input).
17 VSS power_in Digital power ground for the digital circuits, I/O pins and LDO.
18 LDO_CAP power_out Output of the internal 1.8 V LDO that supplies the digital core; a 1 µF capacitor must be connected close to this pin.
19 P2.0 bidirectional Port 2 bit 0 general-purpose I/O, also PWM0 output, EBI address/data bit AD8, and used with PWM mode on LQFP-48.
20 P2.1 bidirectional Port 2 bit 1 general-purpose I/O, also PWM1 output and EBI address/data bit AD9.
21 P2.2 bidirectional Port 2 bit 2 general-purpose I/O, also PWM2 output and EBI address/data bit AD10.
22 P2.3 bidirectional Port 2 bit 3 general-purpose I/O, also PWM3 output and EBI address/data bit AD11.
23 P2.4 bidirectional Port 2 bit 4 general-purpose I/O, also PWM4 output, EBI address/data bit AD12, and I2C1 clock SCL1 (open-drain).
24 P4.0 bidirectional Port 4 bit 0 general-purpose I/O, also PWM0 output (PWM0 on Port 4 alternate) and Timer2 external capture/reset T2EX.
25 P2.5 bidirectional Port 2 bit 5 general-purpose I/O, also PWM5 output, EBI address/data bit AD13, and I2C1 data SDA1 (open-drain).
26 P2.6 bidirectional Port 2 bit 6 general-purpose I/O, also PWM6 output, EBI address/data bit AD14, and comparator 1 output ACMP1_O.
27 P2.7 bidirectional Port 2 bit 7 general-purpose I/O, also PWM7 output and EBI address/data bit AD15.
28 P4.4 bidirectional Port 4 bit 4 general-purpose I/O, also EBI chip select nCS and I2C1 clock SCL1 (open-drain).
29 P4.5 bidirectional Port 4 bit 5 general-purpose I/O, also EBI address latch enable ALE and I2C1 data SDA1 (open-drain).
30 P4.6 bidirectional Port 4 bit 6 general-purpose I/O, also ICE/JTAG debug clock ICE_CLK.
31 P4.7 bidirectional Port 4 bit 7 general-purpose I/O, also ICE/JTAG debug data ICE_DAT.
32 P0.7 bidirectional Port 0 bit 7 general-purpose I/O, also SPI1 clock SPICLK1 and EBI address/data bit AD7.
33 P0.6 bidirectional Port 0 bit 6 general-purpose I/O, also SPI1 MISO_1 and EBI address/data bit AD6.
34 P0.5 bidirectional Port 0 bit 5 general-purpose I/O, also SPI1 MOSI_1 and EBI address/data bit AD5.
35 P0.4 bidirectional Port 0 bit 4 general-purpose I/O, also SPI1 slave select SPISS1 and EBI address/data bit AD4.
36 P4.1 bidirectional Port 4 bit 1 general-purpose I/O, also PWM1 output and Timer3 external capture/reset T3EX.
37 P0.3 bidirectional Port 0 bit 3 general-purpose I/O, also UART0 RTS0 (request to send), EBI address/data bit AD3, and UART0 RXD.
38 P0.2 bidirectional Port 0 bit 2 general-purpose I/O, also UART0 CTS0 (clear to send), EBI address/data bit AD2, and UART0 TXD.
39 P0.1 bidirectional Port 0 bit 1 general-purpose I/O, also UART1 RTS1, EBI address/data bit AD1, UART1 RXD1, and comparator 3 negative input ACMP3_N.
40 P0.0 bidirectional Port 0 bit 0 general-purpose I/O, also UART1 CTS1, EBI address/data bit AD0, UART1 TXD1, and comparator 3 positive input ACMP3_P.
41 VDD power_in Main supply input (2.5 V to 5.5 V) for the internal PLL, digital circuits, I/O ports and LDO.
42 AVDD power_in Analog supply input for the ADC, comparators and analog blocks; must equal VDD to avoid leakage.
43 P1.0 bidirectional Port 1 bit 0 general-purpose I/O, also Timer2 event counter/toggle output T2, ADC input AIN0, and EBI write strobe nWRL.
44 P1.1 bidirectional Port 1 bit 1 general-purpose I/O, also Timer3 event counter/toggle output T3, ADC input AIN1, and EBI write strobe nWRH.
45 P1.2 bidirectional Port 1 bit 2 general-purpose I/O, also UART1 RXD1 and ADC input AIN2.
46 P1.3 bidirectional Port 1 bit 3 general-purpose I/O, also UART1 TXD1 and ADC input AIN3.
47 P1.4 bidirectional Port 1 bit 4 general-purpose I/O, also SPI0 slave select SPISS0, ADC input AIN4, and comparator 0 negative input ACMP0_N.
48 P4.2 bidirectional Port 4 bit 2 general-purpose I/O, also PWM2 output.

Key specifications

Parameter Value
Manufacturer Nuvoton Tech
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply voltage (VDD - VSS) VDD − VSS -0.3 7 V 52
Crystal frequency 1/tCLCL 4 24 MHz 52
Operating temperature TA -40 85 ℃ 52
Storage temperature TST -55 150 ℃ 52
Maximum inflow current into VDD IDD 120 mA 52
Maximum outflow current from VSS ISS 120 mA 52
Maximum sink current, single pin IIO 35 mA 52
Maximum source current, single pin IIO 35 mA 52
Maximum sum of sink currents, all pins IIO 100 mA 52
Maximum sum of output currents, all pins IIO 100 mA 52
Operating voltage VDD 2.5 5.5 V VDD = 2.5 V ~ 5.5 V up to 50 MHz 53
Ground (VSS / AVSS) VSS / AVSS -0.3 V 53
LDO output voltage VLDO 1.62 1.8 1.98 V VDD ≥ 2.5 V 53
Bandgap voltage VBG 1.16 1.2 1.24 V VDD = 2.5 V ~ 5.5 V, TA = 25°C 53
Bandgap voltage VBG 1.14 1.2 1.26 V VDD = 2.5 V ~ 5.5 V, TA = -40°C~85°C 53
Allowed difference between VDD and AVDD VDD−AVDD -0.3 0 0.3 V 53
Logic 0 input current, P0/1/2/3/4 (quasi-bidirectional) IIL -65 -75 µA VDD = 5.5 V, VIN = 0V 54
Logic 1-to-0 transition output current, P0/1/2/3/4 (quasi-bidirectional) ITL -690 -750 µA VDD = 5.5 V, VIN = 2.0V 55
P0/1/2/3/4 input leakage current ILK -1 1 µA VDD = 5.5 V, 0 < VIN < VDD; Open-drain or input only mode 55
P0/1/2/3/4 input low voltage (TTL input) VIL1 -0.3 0.8 V VDD = 4.5 V 55
P0/1/2/3/4 input low voltage (TTL input) VIL1 -0.3 0.6 V VDD = 2.5 V 55
P0/1/2/3/4 input high voltage (TTL input) VIH1 2 V VDD = 5.5 V 55
P0/1/2/3/4 input high voltage (TTL input) VIH1 1.5 V VDD = 3.0 V 55
XT1 input low voltage (CMOS input) VIL3 0 0.8 V VDD = 4.5 V 55
XT1 input low voltage (CMOS input) VIL3 0 0.4 V VDD = 2.5 V 55
XT1 input high voltage (CMOS input) VIH3 3.5 V VDD = 5.5 V 55
XT1 input high voltage (CMOS input) VIH3 2.4 V VDD = 3.0 V 55
/RESET pin negative-going threshold voltage (Schmitt input) VILS -0.3 V 55
/RST pin internal pull-up resistance RRST 40 150 kΩ 55
P0/1/2/3/4 negative-going threshold voltage (Schmitt input) VILS -0.3 V 55
P0/1/2/3/4 source current (quasi-bidirectional) ISR11 -300 -420 µA VDD = 4.5 V, VS = 2.4 V 55
P0/1/2/3/4 source current (quasi-bidirectional) ISR12 -50 -75 µA VDD = 2.7 V, VS = 2.2 V 55
P0/1/2/3/4 source current (quasi-bidirectional) ISR13 -40 -67 µA VDD = 2.5 V, VS = 2.0 V 55
P0/1/2/3/4 source current (push-pull) ISR21 -20 -26 mA VDD = 4.5 V, VS = 2.4 V 55
P0/1/2/3/4 source current (push-pull) ISR22 -3 -5 mA VDD = 2.7 V, VS = 2.2 V 55
P0/1/2/3/4 source current (push-pull) ISR23 -2.5 -4.2 mA VDD = 2.5 V, VS = 2.0 V 55
P0/1/2/3/4 sink current (quasi-bidirectional and push-pull) ISK11 10 16 mA VDD = 4.5 V, VS = 0.45 V 55
P0/1/2/3/4 sink current (quasi-bidirectional and push-pull) ISK12 6 9 mA VDD = 2.7 V, VS = 0.45 V 55
P0/1/2/3/4 sink current (quasi-bidirectional and push-pull) ISK13 5 8 mA VDD = 2.5 V, VS = 0.45 V 55
Clock high time tCHCX 10 ns 56
Clock low time tCLCX 10 ns 56
Clock rise time tCLCH 2 15 ns 56
Clock fall time tCHCL 2 15 ns 56
External oscillator input clock voltage VHXT 2.5 5.5 V 56
External oscillator temperature TA -40 85 ℃ 56
External oscillator input clock frequency fHXT 4 24 MHz 56
Internal 22.1184 MHz RC oscillator voltage VHRC 1.62 1.8 1.98 V 57
Internal 22.1184 MHz RC oscillator frequency tolerance fHRC -1 1 % After calibration, TA = 25 ℃, VDD = 5 V 57
Internal 22.1184 MHz RC oscillator frequency tolerance fHRC -3 3 % TA = -40 ℃ ~ 85 ℃, VDD = 2.5 V ~ 5.5 V 57
Internal 10 kHz RC oscillator voltage VLRC 2.5 5.5 V 57
Internal 10 kHz RC oscillator frequency tolerance fLRC -10 10 % After calibration, VDD = 2.5 V ~ 5.5 V, TA = 25℃ 57
Internal 10 kHz RC oscillator frequency tolerance fLRC -40 40 % VDD = 2.5 V ~ 5.5 V, TA = -40℃ ~ +85℃ 57
Flash operating voltage VFLA 1.62 1.8 1.98 V 63
Data retention TRET 10 year TA = 85℃ 63

CAD (KiCad official)

  • Symbol: M0516LDN
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: m0516ldn-etched.step / m0516ldn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m0516ldn.step / m0516ldn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nuvoton Tech datasheet (80 pp, sha256 dad0af4ccae67bcc, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF