# LX7167CLD-TR

**Microchip Tech** · DC-DC Converters · WDFN-8(2x2)

LX7167CLD-TR from Microchip Tech, in a WDFN-8(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Ground pin for the power stage. |
| 2 | SW | output | Switch-node pin connecting the output inductor to the output capacitor; when the chip is disabled the internal discharge resistor (80 to 1400 Ohm) discharges the output capacitance through this pin. |
| 3 | GND | power_in | Ground pin. |
| 4 | FB | input | Voltage feedback pin, connected through a resistor divider to set the output voltage; the reference is 0.6V with a range of 0.591V to 0.609V over -10°C to 85°C. |
| 5 | EN | input | Pulling this pin above 1V enables the controller, and pulling it low turns the IC off and enables the internal discharge FET. |
| 6 | PG | output | Open-drain power-good output that requires an external pull-up resistor and goes high when FB reaches the power good threshold after soft start has finished. |
| 7 | VCC | power_in | Analog input voltage terminal, connected to VIN through a 10 ohm resistor with a 1µF ceramic capacitor from VCC to GND. |
| 8 | PVIN | power_in | Input voltage terminal of the regulator, requiring a minimum 10µF X5R ceramic capacitor placed as close as possible to this pin and the PGND plane; the operating range is 3V to 5.5V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | WDFN-8(2x2) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| PVIN, EN, FB, PG to GND |  | -0.3 |  | 7 | V |  | 4 |
| SW to GND |  | -0.3 |  | 7 | V |  | 4 |
| SW to GND (shorter than 50ns) |  | -2 |  | 7 | V | Shorter than 50ns | 4 |
| Junction Temperature |  | 0 |  | 150 | °C |  | 4 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 4 |
| VCC, PVIN |  | 3 |  | 5.5 | V |  | 4 |
| VOUT | VOUT | 0.6 |  |  | V | Maximum printed as VIN, 0.5 | 4 |
| Ambient Temperature |  | -10 |  | 85 | °C |  | 4 |
| Output Current |  | 0 |  | 2.4 | A |  | 4 |
| Input Current | IQ |  |  | 350 | µA | ILOAD = 0 | 4 |
| Input Current at Shut Down | ISHDN |  | 0.1 | 2 | µA | VEN = GND | 4 |
| PVIN Under Voltage Lockout |  | 2.4 |  | 2.8 | V | PVIN rising | 4 |
| UVLO Hysteresis |  |  | 260 |  | mV |  | 4 |
| Feedback Voltage | VREF | 0.594 | 0.6 | 0.606 | V | TA = 25°C | 5 |
| Feedback Voltage | VREF | 0.591 |  | 0.609 | V | -10°C to 85°C | 5 |
| FB Pin Input Current | IFB |  |  | 10 | nA |  | 5 |
| Line Regulation |  |  | 0.7 |  | % | PVIN from 3V to 5.5V | 5 |
| Load Regulation |  |  | 1 |  | %/A | ILOAD = 0 to 2A. Note 1 | 5 |
| FB UVLO Threshold | VFBUVLO |  | 70 |  | %VREF |  | 5 |
| RDSON of High Side | RDSON_H |  | 95 | 150 | mΩ |  | 5 |
| RDSON of Low Side | RDSON_L |  | 75 | 100 | mΩ |  | 5 |
| Peak Current Limit | IL | 2.6 | 3.5 | 4.5 | A |  | 5 |
| Thermal Shutdown Threshold | TSH |  | 150 |  | °C |  | 5 |
| Thermal Shutdown Hysteresis | TH |  | 20 |  | °C |  | 5 |
| OVPR Rising Threshold | OVPR |  | 6.1 |  | V |  | 5 |
| OVPF Falling Threshold | OVPF |  | 5.5 |  | V |  | 5 |
| Switching Frequency | f | 2.6 | 3 | 3.4 | MHz |  | 5 |
| Soft Start Time | TSS |  | 500 |  | µs | From EN High to VOUT reach regulation | 5 |
| Hiccup Time | THICCUP |  | 1.2 |  | ms | VFB = 0.2V | 5 |
| Input High | ENVIN | 1 |  |  | V |  | 5 |
| Input Low | ENVIL |  |  | 0.4 | V |  | 5 |
| EN Hysteresis | ENH |  | 0.1 |  | V |  | 5 |
| Input Bias | ENII |  | 0.01 | 1 | µA |  | 5 |
| Power Good Transition High Threshold | VPG |  | 83 |  | % |  | 5 |
| Hysteresis | VPGHY |  | 40 |  | mV | Either VFB rising or falling | 5 |
| Power Good Internal FET RDSON | PGRDSON |  | 100 | 300 | Ω | VCC = 5V | 5 |
| PG FET Leakage Current |  |  | 0.01 | 1 | µA |  | 5 |
| PG internal Glitch Filter |  |  | 5 |  | µs | Note 1 | 5 |
| Internal Discharge Resistor |  | 80 | 200 | 1400 | Ω |  | 5 |
| Thermal Resistance θJA | θJA |  | 75 |  | °C/W | Four-layer board per JESD-51; no forced airflow | 4 |

## CAD (KiCad official)

- Symbol: `LX7167CLD-TR`
- Footprint: `Package_DFN_QFN:WDFN-8-1EP_2x2mm_P0.5mm_EP0.8x1.2mm`
- 3D model: WDFN-8(2x2) (KiCad packages3D, STEP)
- 3D model files: `lx7167cld-tr-etched.step` / `lx7167cld-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lx7167cld-tr.step` / `lx7167cld-tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/lx7167cld-tr-datasheet.pdf) (12 pp, sha256 `ec7699f4a21ec585`, retrieved 2026-11-02, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lx7167cld-tr-datasheet.pdf)