component
LW5912N23D
Public Made by Adomby adom
Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLW5912N23D
Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
LW5912N23D from Lewa Micro, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin for the LDO; on the SOT23-3L package it is the ground reference, and the datasheet asks for separate VIN and VOUT ground planes that connect only at this GND pin. |
| 2 | VOUT | power_out | Regulated output pin (0.8 V to 5.0 V, 0 to 400 mA per the recommended operating range); connect a low-ESR capacitor, at least 1 µF, from OUT to GND, and an internal pulldown discharges OUT when EN is low. |
| 3 | VIN | power_in | Input supply pin, rated 1.6 V to 7.0 V in the recommended operating range (absolute maximum -0.3 V to 9.0 V); use the recommended or larger ceramic input capacitor from IN to ground, placed as close to the device as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | VOUT | -1.5 | 1.5 | % | IOUT= 1mA | 5 | |
| Current Limit | ILIM | 410 | 530 | mA | 5 | ||
| Quiescent Current | IQ | 0.65 | 1 | μA | VIN= VEN= VOUT +1V, No Load | 5 | |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | 0.1 | 0.3 | %/V | VIN= VOUT +1.0V to 7.0V, IOUT=1mA | 5 | |
| Load Regulation | ΔVOUT | 30 | 70 | mV | 1mA≤IOUT≤400mA | 5 | |
| Input Voltage (recommended operating) | VIN | 1.6 | 7 | V | 4 | ||
| EN Pin Voltage (recommended operating) | VEN | 0 | 7 | V | 4 | ||
| Output Current (recommended operating) | IOUT | 0 | 400 | mA | 4 | ||
| Junction Temperature Range (recommended operating) | TJ | -40 | 125 | ℃ | 4 | ||
| VIN Supply Voltage (absolute maximum) | VIN | -0.3 | 9 | V | 4 | ||
| EN Pin Voltage (absolute maximum) | VEN | -0.3 | 9 | V | 4 | ||
| VOUT pin Voltage (upper limit VIN+0.3) | VOUT | -0.3 | V | upper limit printed as (VIN+0.3) | 4 | ||
| ESD Susceptibility, HBM | V(ESD) | -4000 | 4000 | V | per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Junction Temperature Range (absolute maximum) | TJ | -40 | 150 | ℃ | 4 | ||
| Storage Temperature Range | TSTG | -40 | 150 | ℃ | 4 | ||
| Lead Temperature (Soldering) | TSOLDER | 260 | ℃ | 10s | 4 | ||
| Junction-to-ambient Thermal Resistance (SOT23-3L) | RθJA | 330 | ℃/W | Device mounted on FR-4 PCB, per JESD51-3 | 4 |
CAD (KiCad official)
- Symbol:
LW5912N23D - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files:
lw5912n23d-etched.step/lw5912n23d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lw5912n23d.step/lw5912n23d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (25 pp, sha256
53294d4f1daeb984, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).