component
LW5412A23E
Public Made by Adomby adom
Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LW5412A23E
Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5L
LW5412A23E from Lewa Micro, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input pin supplying the LDO over the recommended 1.9 V to 5.5 V range; use the recommended or larger ceramic input capacitor from IN to ground, placed as close to the device as possible. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin: drive above VEN(HI) (1.5 V) to turn the regulator on and below VEN(LO) (0.5 V) to put it in shutdown; recommended EN pin voltage range is 0 to 5.5 V. |
| 4 | NC | unconnected | No internal connection; the datasheet says to ground this pin for better thermal performance. |
| 5 | VOUT | power_out | Regulated output (1.2 V to 5.0 V, fixed by laser trim for this part's 1.2 V option) rated for 0 to 500 mA; use a low-ESR capacitor of the nominal recommended value or larger from OUT to GND, and an internal pulldown discharges OUT in shutdown. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 1.9 | 5.5 | V | 5 | ||
| Output Accuracy | VOUT | -1 | 1 | % | IOUT= 1mA | 5 | |
| Current Limit | ILIM | 550 | 700 | mA | 5 | ||
| Quiescent Current | IQ | 10 | 15 | μA | VIN= VEN=VOUT+1V, No Load | 5 | |
| Shutdown Current | ISHD | 0.1 | μA | VEN=0V | 5 | ||
| Dropout Voltage | VDROP | 110 | mV | IOUT=100mA, VOUT=1.2V | 5 | ||
| Dropout Voltage | VDROP | 510 | mV | IOUT=500mA, VOUT=1.2V | 5 | ||
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | 0.05 | 0.25 | %/V | VIN= VOUT +1V to 5.5V, IOUT=1mA | 5 | |
| Load Regulation | ΔVOUT | 20 | 60 | mV | 1mA≤IOUT≤500mA | 5 | |
| Short Current | ISHORT | 50 | mA | VOUT=0V | 5 | ||
| EN Pull-Down Current | IEN | 0.15 | μA | VIN=VEN =5.5V | 5 | ||
| EN High Voltage | VENH | 1.5 | V | VIN=1.9V to 5.5V, IOUT=1mA | 5 | ||
| EN Low Voltage | VENL | 0.5 | V | 5 | |||
| Thermal Shutdown Temperature | TSD | 160 | ℃ | Temperature rising | 5 | ||
| TSD Hysteresis | △TSD | 20 | ℃ | Temperature falling | 5 | ||
| Output Discharge Resistance | RDSCHG | 60 | Ω | VIN=5.5V, VEN=0V | 5 | ||
| Supply Voltage | VIN | -0.3 | 6.5 | V | 4 | ||
| EN Pin Voltage | VEN | -0.3 | 6.5 | V | 4 | ||
| VOUT Pin Voltage | VOUT | -0.3 | 6 | V | 4 | ||
| ESD Susceptibility | V(ESD) | -4000 | 4000 | V | HBM, per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Junction Temperature Range | TJ | -40 | 150 | ℃ | 4 | ||
| Storage Temperature Range | TSTG | -40 | 150 | ℃ | 4 | ||
| Lead Temperature (Soldering) | TSOLDER | 260 | ℃ | 10s | 4 | ||
| Junction-to-ambient Thermal Resistance (SOT23-5L) | RθJA | 188 | ℃/W | Device mounted on FR-4 PCB, JESD51-3 | 4 | ||
| VIN Supply Voltage (recommended) | VIN | 1.9 | 5.5 | V | 4 | ||
| EN Pin Voltage (recommended) | VEN | 0 | 5.5 | V | 4 | ||
| VOUT Pin Voltage (recommended) | VOUT | 1.2 | 5 | V | Series range; listed for LW54XX family | 4 | |
| Output Current | IOUT | 0 | 500 | mA | 4 | ||
| Junction Temperature Range (recommended) | TJ | -40 | 125 | ℃ | 4 |
CAD (KiCad official)
- Symbol:
LW5412A23E - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
lw5412a23e-etched.step/lw5412a23e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lw5412a23e.step/lw5412a23e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (23 pp, sha256
df31c2e49d16aac8, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LW5412A23E
**Lewa Micro** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5L
LW5412A23E from Lewa Micro, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input pin supplying the LDO over the recommended 1.9 V to 5.5 V range; use the recommended or larger ceramic input capacitor from IN to ground, placed as close to the device as possible. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin: drive above VEN(HI) (1.5 V) to turn the regulator on and below VEN(LO) (0.5 V) to put it in shutdown; recommended EN pin voltage range is 0 to 5.5 V. |
| 4 | NC | unconnected | No internal connection; the datasheet says to ground this pin for better thermal performance. |
| 5 | VOUT | power_out | Regulated output (1.2 V to 5.0 V, fixed by laser trim for this part's 1.2 V option) rated for 0 to 500 mA; use a low-ESR capacitor of the nominal recommended value or larger from OUT to GND, and an internal pulldown discharges OUT in shutdown. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 1.9 | | 5.5 | V | | 5 |
| Output Accuracy | VOUT | -1 | | 1 | % | IOUT= 1mA | 5 |
| Current Limit | ILIM | 550 | 700 | | mA | | 5 |
| Quiescent Current | IQ | | 10 | 15 | μA | VIN= VEN=VOUT+1V, No Load | 5 |
| Shutdown Current | ISHD | | 0.1 | | μA | VEN=0V | 5 |
| Dropout Voltage | VDROP | | 110 | | mV | IOUT=100mA, VOUT=1.2V | 5 |
| Dropout Voltage | VDROP | | 510 | | mV | IOUT=500mA, VOUT=1.2V | 5 |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | | 0.05 | 0.25 | %/V | VIN= VOUT +1V to 5.5V, IOUT=1mA | 5 |
| Load Regulation | ΔVOUT | | 20 | 60 | mV | 1mA≤IOUT≤500mA | 5 |
| Short Current | ISHORT | | 50 | | mA | VOUT=0V | 5 |
| EN Pull-Down Current | IEN | | 0.15 | | μA | VIN=VEN =5.5V | 5 |
| EN High Voltage | VENH | | 1.5 | | V | VIN=1.9V to 5.5V, IOUT=1mA | 5 |
| EN Low Voltage | VENL | | 0.5 | | V | | 5 |
| Thermal Shutdown Temperature | TSD | | 160 | | ℃ | Temperature rising | 5 |
| TSD Hysteresis | △TSD | | 20 | | ℃ | Temperature falling | 5 |
| Output Discharge Resistance | RDSCHG | | 60 | | Ω | VIN=5.5V, VEN=0V | 5 |
| Supply Voltage | VIN | -0.3 | | 6.5 | V | | 4 |
| EN Pin Voltage | VEN | -0.3 | | 6.5 | V | | 4 |
| VOUT Pin Voltage | VOUT | -0.3 | | 6 | V | | 4 |
| ESD Susceptibility | V(ESD) | -4000 | | 4000 | V | HBM, per ANSI/ESDA/JEDEC JS-001 | 4 |
| Junction Temperature Range | TJ | -40 | | 150 | ℃ | | 4 |
| Storage Temperature Range | TSTG | -40 | | 150 | ℃ | | 4 |
| Lead Temperature (Soldering) | TSOLDER | | | 260 | ℃ | 10s | 4 |
| Junction-to-ambient Thermal Resistance (SOT23-5L) | RθJA | | 188 | | ℃/W | Device mounted on FR-4 PCB, JESD51-3 | 4 |
| VIN Supply Voltage (recommended) | VIN | 1.9 | | 5.5 | V | | 4 |
| EN Pin Voltage (recommended) | VEN | 0 | | 5.5 | V | | 4 |
| VOUT Pin Voltage (recommended) | VOUT | 1.2 | | 5 | V | Series range; listed for LW54XX family | 4 |
| Output Current | IOUT | 0 | | 500 | mA | | 4 |
| Junction Temperature Range (recommended) | TJ | -40 | | 125 | ℃ | | 4 |
## CAD (KiCad official)
- Symbol: `LW5412A23E`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `lw5412a23e-etched.step` / `lw5412a23e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lw5412a23e.step` / `lw5412a23e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Lewa Micro datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758027049150242816) (23 pp, sha256 `df31c2e49d16aac8`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lw5412a23e-datasheet.pdf)