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LW5230N23D

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Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LW5230N23D

Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

LW5230N23D from Lewa Micro, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin; the datasheet recommends separate VIN and VOUT ground planes connected only at this GND pin.
2 VOUT power_out Regulated output voltage pin (1.2V to 5.0V, 500mA maximum output current); connect a low-ESR capacitor of at least 1µF from OUT to GND, and an internal pulldown discharges OUT when VEN < VEN(LOW).
3 VIN power_in Input supply pin, rated 1.5V to 6.0V, to be decoupled with the recommended ceramic capacitor from IN to ground and placed as close to the device as possible.

Key specifications

Parameter Value
Manufacturer Lewa Micro
Package SOT-23-3L
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage (electrical characteristics) VIN 1.5 6 V 5
Output Accuracy VOUT -1.5 1.5 % IOUT= 1mA 5
Current Limit ILIM 515 700 mA 5
Quiescent Current IQ 40 60 μA VIN= VEN=VOUT+1V, No Load 5
Line Regulation ΔVOUT/(ΔVIN*VOUT(NOM)) 0.1 0.25 %/V VIN= VOUT +1V to 6V, IOUT=1mA 5
Load Regulation ΔVOUT 20 50 mV 1mA≤IOUT≤500mA 5
Absolute max VIN Supply Voltage VIN -0.3 7 V 4
Absolute max EN Pin Voltage VEN -0.3 7 V 4
Absolute max VOUT Pin Voltage VOUT -0.3 V upper limit printed as (VIN+0.3) 4
ESD Susceptibility, HBM V(ESD) -4000 4000 V per ANSI/ESDA/JEDEC JS-001 4
Junction Temperature Range (absolute max) TJ -40 150 ℃ 4
Storage Temperature Range TSTG -40 150 ℃ 4
Lead Temperature (Soldering) TSOLDER 260 ℃ 10s 4
VIN Supply Voltage (recommended) VIN 1.5 6 V 4
EN Pin Voltage (recommended) VEN 0 6 V 4
VOUT Pin Voltage (recommended) VOUT 1.2 5 V 4
Output Current (recommended) IOUT 0 500 mA 4
Junction Temperature Range (recommended) TJ -40 125 ℃ 4
Shutdown Current ISHD 0.1 μA VIN=6.0, VEN=0V 5
Short Current ISHORT 80 mA VOUT=0V 5
EN High Voltage VENH 1.5 V VIN=1.5V to 6.0V, IOUT=1mA 5
EN Low Voltage VENL 0.5 V 5
Startup Time TSTR 25 μs From VEN 'L'→'H' to 95%*VOUT, COUT=1uF, No Load 5
Power Supply Rejection Ratio PSRR 85 dB VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=217Hz 5
Power Supply Rejection Ratio PSRR 95 dB VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=1KHz 5
Power Supply Rejection Ratio PSRR 75 dB VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=10KHz 5
Power Supply Rejection Ratio PSRR 55 dB VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=100KHz 5
Thermal Shutdown Temperature TSD 160 ℃ Temperature rising 5
TSD Hysteresis △TSD 20 ℃ Temperature falling 5
Output Discharge Resistance RDSCHG 150 Ω VIN=6V, VEN=0V 5
Junction-to-ambient Thermal Resistance, SOT23-3L RθJA 290 ℃/W Device mounted on FR-4 PCB, refer to JESD51-3 4

CAD (KiCad official)

  • Symbol: LW5230N23D
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: lw5230n23d-etched.step / lw5230n23d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lw5230n23d.step / lw5230n23d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lewa Micro datasheet (22 pp, sha256 554585e66fced619, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF