component
LW5230N11E
Public Made by Adomby adom
Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-4L(1x1). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LW5230N11E
Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4L(1x1)
LW5230N11E from Lewa Micro, in a DFN-4L(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output pin that needs a low-ESR ceramic capacitor of at least 1µF from OUT to GND, and an internal pulldown discharges OUT in shutdown (VEN < VEN(LOW)); output range is 1.2 V to 5.0 V. |
| 2 | GND | power_in | Ground pin; the datasheet recommends separate VIN and VOUT ground planes that connect only at this GND pin. |
| 3 | EN | input | Enable pin: drive above VEN(HI) (1.5 V min) to turn the regulator on and below VEN(LO) (0.5 V) to put it into shutdown, with an EN pin voltage range of 0 to 6.0 V. |
| 4 | VIN | power_in | Input supply pin with a recommended operating range of 1.5 V to 6.0 V (absolute maximum -0.3 V to 7.0 V), decoupled with a ceramic capacitor placed as close to the device as possible. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | DFN-4L(1x1) |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Accuracy | VOUT | -1.5 | 1.5 | % | IOUT= 1mA | 5 | |
| Current Limit | ILIM | 515 | 700 | mA | 5 | ||
| Input Voltage | VIN | 1.5 | 6 | V | 5 | ||
| EN High Voltage | VENH | 1.5 | V | VIN=1.5V to 6.0V, IOUT=1mA | 5 | ||
| EN Low Voltage | VENL | 0.5 | V | 5 | |||
| Quiescent Current | IQ | 40 | 60 | μA | VIN= VEN=VOUT+1V, No Load | 5 | |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | 0.1 | 0.25 | %/V | VIN= VOUT +1V to 6V, IOUT=1mA | 5 | |
| Load Regulation | ΔVOUT | 20 | 50 | mV | 1mA≤IOUT≤500mA | 5 | |
| Input Voltage (absolute maximum) | VIN | -0.3 | 7 | V | Supply voltage | 4 | |
| EN Pin Voltage (absolute maximum) | VEN | -0.3 | 7 | V | 4 | ||
| VOUT Pin Voltage (absolute maximum) | VOUT | -0.3 | V | Printed as -0.3~(VIN+0.3); upper limit is VIN+0.3 V, not a number | 4 | ||
| ESD Susceptibility HBM | V(ESD) | -4000 | 4000 | V | Per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Junction Temperature Range (absolute maximum) | TJ | -40 | 150 | ℃ | 4 | ||
| Storage Temperature Range | TSTG | -40 | 150 | ℃ | 4 | ||
| Lead Temperature (Soldering) | TSOLDER | 260 | ℃ | 10s | 4 | ||
| VIN Supply Voltage (recommended) | VIN | 1.5 | 6 | V | 4 | ||
| EN Pin Voltage (recommended) | VEN | 0 | 6 | V | 4 | ||
| VOUT Pin Voltage (recommended, family range) | VOUT | 1.2 | 5 | V | LW52XX family range | 4 | |
| Output Current | IOUT | 0 | 500 | mA | 4 | ||
| Junction Temperature Range (recommended) | TJ | -40 | 125 | ℃ | 4 | ||
| Junction-to-ambient Thermal Resistance | RθJA | 280 | ℃/W | DFN1x1-4L; device on FR-4 PCB per JESD51-3 | 4 | ||
| Startup Time | TSTR | 25 | μs | From VEN 'L'→'H' to 95%*VOUT, COUT=1uF, No Load | 5 | ||
| Shutdown Current | ISHD | 0.1 | μA | VIN=6.0, VEN=0V | 5 | ||
| Short Current | ISHORT | 80 | mA | VOUT=0V | 5 | ||
| Power Supply Rejection Ratio | PSRR | 85 | dB | f=217Hz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 | ||
| Power Supply Rejection Ratio | PSRR | 95 | dB | f=1KHz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 | ||
| Power Supply Rejection Ratio | PSRR | 75 | dB | f=10KHz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 | ||
| Power Supply Rejection Ratio | PSRR | 55 | dB | f=100KHz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 | ||
| Thermal Shutdown Temperature | TSD | 160 | ℃ | Temperature rising | 5 | ||
| TSD Hysteresis | △TSD | 20 | ℃ | Temperature falling | 5 | ||
| Output Discharge Resistance | RDSCHG | 150 | Ω | VIN=6V, VEN=0V | 5 |
CAD (KiCad official)
- Symbol:
LW5230N11E - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN-4L(1x1) (KiCad packages3D, STEP)
- 3D model files:
lw5230n11e-etched.step/lw5230n11e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lw5230n11e.step/lw5230n11e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (22 pp, sha256
554585e66fced619, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LW5230N11E
**Lewa Micro** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4L(1x1)
LW5230N11E from Lewa Micro, in a DFN-4L(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated output pin that needs a low-ESR ceramic capacitor of at least 1µF from OUT to GND, and an internal pulldown discharges OUT in shutdown (VEN < VEN(LOW)); output range is 1.2 V to 5.0 V. |
| 2 | GND | power_in | Ground pin; the datasheet recommends separate VIN and VOUT ground planes that connect only at this GND pin. |
| 3 | EN | input | Enable pin: drive above VEN(HI) (1.5 V min) to turn the regulator on and below VEN(LO) (0.5 V) to put it into shutdown, with an EN pin voltage range of 0 to 6.0 V. |
| 4 | VIN | power_in | Input supply pin with a recommended operating range of 1.5 V to 6.0 V (absolute maximum -0.3 V to 7.0 V), decoupled with a ceramic capacitor placed as close to the device as possible. |
| 5 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | DFN-4L(1x1) |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Accuracy | VOUT | -1.5 | | 1.5 | % | IOUT= 1mA | 5 |
| Current Limit | ILIM | 515 | | 700 | mA | | 5 |
| Input Voltage | VIN | 1.5 | | 6 | V | | 5 |
| EN High Voltage | VENH | 1.5 | | | V | VIN=1.5V to 6.0V, IOUT=1mA | 5 |
| EN Low Voltage | VENL | | | 0.5 | V | | 5 |
| Quiescent Current | IQ | | 40 | 60 | μA | VIN= VEN=VOUT+1V, No Load | 5 |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | | 0.1 | 0.25 | %/V | VIN= VOUT +1V to 6V, IOUT=1mA | 5 |
| Load Regulation | ΔVOUT | | 20 | 50 | mV | 1mA≤IOUT≤500mA | 5 |
| Input Voltage (absolute maximum) | VIN | -0.3 | | 7 | V | Supply voltage | 4 |
| EN Pin Voltage (absolute maximum) | VEN | -0.3 | | 7 | V | | 4 |
| VOUT Pin Voltage (absolute maximum) | VOUT | -0.3 | | | V | Printed as -0.3~(VIN+0.3); upper limit is VIN+0.3 V, not a number | 4 |
| ESD Susceptibility HBM | V(ESD) | -4000 | | 4000 | V | Per ANSI/ESDA/JEDEC JS-001 | 4 |
| Junction Temperature Range (absolute maximum) | TJ | -40 | | 150 | ℃ | | 4 |
| Storage Temperature Range | TSTG | -40 | | 150 | ℃ | | 4 |
| Lead Temperature (Soldering) | TSOLDER | | | 260 | ℃ | 10s | 4 |
| VIN Supply Voltage (recommended) | VIN | 1.5 | | 6 | V | | 4 |
| EN Pin Voltage (recommended) | VEN | 0 | | 6 | V | | 4 |
| VOUT Pin Voltage (recommended, family range) | VOUT | 1.2 | | 5 | V | LW52XX family range | 4 |
| Output Current | IOUT | 0 | | 500 | mA | | 4 |
| Junction Temperature Range (recommended) | TJ | -40 | | 125 | ℃ | | 4 |
| Junction-to-ambient Thermal Resistance | RθJA | | 280 | | ℃/W | DFN1x1-4L; device on FR-4 PCB per JESD51-3 | 4 |
| Startup Time | TSTR | | 25 | | μs | From VEN 'L'→'H' to 95%*VOUT, COUT=1uF, No Load | 5 |
| Shutdown Current | ISHD | | 0.1 | | μA | VIN=6.0, VEN=0V | 5 |
| Short Current | ISHORT | | 80 | | mA | VOUT=0V | 5 |
| Power Supply Rejection Ratio | PSRR | | 85 | | dB | f=217Hz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 |
| Power Supply Rejection Ratio | PSRR | | 95 | | dB | f=1KHz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 |
| Power Supply Rejection Ratio | PSRR | | 75 | | dB | f=10KHz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 |
| Power Supply Rejection Ratio | PSRR | | 55 | | dB | f=100KHz; VIN=4.3V, VOUT=3.3V, CIN=None, VPP=0.5V, IOUT=10mA | 5 |
| Thermal Shutdown Temperature | TSD | | 160 | | ℃ | Temperature rising | 5 |
| TSD Hysteresis | △TSD | | 20 | | ℃ | Temperature falling | 5 |
| Output Discharge Resistance | RDSCHG | | 150 | | Ω | VIN=6V, VEN=0V | 5 |
## CAD (KiCad official)
- Symbol: `LW5230N11E`
- Footprint: `Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm`
- 3D model: DFN-4L(1x1) (KiCad packages3D, STEP)
- 3D model files: `lw5230n11e-etched.step` / `lw5230n11e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lw5230n11e.step` / `lw5230n11e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Lewa Micro datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8775070434226524160) (22 pp, sha256 `554585e66fced619`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lw5230n11e-datasheet.pdf)