component
LW5228N23D
Public Made by Adomby adom
Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLW5228N23D
Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
LW5228N23D from Lewa Micro, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; the datasheet asks for separate VIN and VOUT ground planes that connect only at this GND pin for best PSRR, noise and transient response. |
| 2 | VOUT | power_out | Regulated output pin (1.2 V to 5.0 V, 500 mA max); connect a low-ESR capacitor of at least the nominal recommended value (1 µF) from OUT to GND, and note an internal pulldown discharges OUT when the regulator is in shutdown. |
| 3 | VIN | power_in | Input supply pin, rated 1.5 V to 6.0 V; use the recommended or larger ceramic capacitor from IN to ground and place it as close to the device as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Input Voltage | VIN | 1.5 | 6 | V | 5 | ||
| Output Accuracy | VOUT | -1.5 | 1.5 | % | IOUT= 1mA | 5 | |
| Current Limit | ILIM | 515 | 700 | mA | Note (1): guaranteed by design | 5 | |
| Quiescent Current | IQ | 40 | 60 | μA | VIN= VEN=VOUT+1V, No Load | 5 | |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | 0.1 | 0.25 | %/V | VIN= VOUT +1V to 6V, IOUT=1mA | 5 | |
| Load Regulation | ΔVOUT | 20 | 50 | mV | 1mA≤IOUT≤500mA | 5 | |
| EN High Voltage | VENH | 1.5 | V | VIN=1.5V to 6.0V, IOUT=1mA | 5 | ||
| EN Low Voltage | VENL | 0.5 | V | 5 | |||
| Absolute Max Supply Voltage | VIN | -0.3 | 7 | V | TA = 25℃ | 4 | |
| Absolute Max EN Pin Voltage | VEN | -0.3 | 7 | V | TA = 25℃ | 4 | |
| Absolute Max VOUT Pin Voltage (upper limit printed as VIN+0.3) | VOUT | -0.3 | V | TA = 25℃; upper limit printed as (VIN+0.3) | 4 | ||
| ESD Susceptibility, HBM | V(ESD) | -4000 | 4000 | V | Per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Absolute Max Lead Temperature (Soldering) | TSOLDER | 260 | ℃ | 10s | 4 | ||
| Absolute Max Junction Temperature Range | TJ | -40 | 150 | ℃ | 4 | ||
| Absolute Max Storage Temperature Range | TSTG | -40 | 150 | ℃ | 4 | ||
| Recommended VIN Supply Voltage | VIN | 1.5 | 6 | V | 4 | ||
| Recommended EN Pin Voltage | VEN | 0 | 6 | V | 4 | ||
| Recommended VOUT Pin Voltage (series range) | VOUT | 1.2 | 5 | V | 4 | ||
| Recommended Output Current | IOUT | 0 | 500 | mA | 4 | ||
| Recommended Junction Temperature Range | TJ | -40 | 125 | ℃ | 4 | ||
| Shutdown Current | ISHD | 0.1 | μA | VIN=6.0, VEN=0V | 5 | ||
| Dropout Voltage at 100mA, 2.8V output | VDROP | 55 | mV | IOUT=100mA, VOUT=2.8V; note (1)(2) | 5 | ||
| Dropout Voltage at 500mA, 2.8V output | VDROP | 280 | mV | IOUT=500mA, VOUT=2.8V; note (1)(2) | 5 | ||
| Short Current | ISHORT | 80 | mA | VOUT=0V; note (1) | 5 | ||
| Startup Time | TSTR | 25 | μs | From VEN 'L'→'H' to 95%*VOUT, COUT=1uF, No Load | 5 | ||
| Power Supply Rejection Ratio at 217Hz | PSRR | 85 | dB | VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=217Hz | 5 | ||
| Power Supply Rejection Ratio at 1KHz | PSRR | 95 | dB | VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=1KHz | 5 | ||
| Power Supply Rejection Ratio at 10KHz | PSRR | 75 | dB | VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=10KHz | 5 | ||
| Power Supply Rejection Ratio at 100KHz | PSRR | 55 | dB | VIN= 4.3V, VOUT=3.3V, CIN =None, VPP=0.5V, IOUT=10mA, f=100KHz | 5 | ||
| Thermal Shutdown Temperature (rising) | TSD | 160 | ℃ | Temperature rising | 5 | ||
| TSD Hysteresis (falling) | ΔTSD | 20 | ℃ | Temperature falling | 5 | ||
| Output Discharge Resistance | RDSCHG | 150 | Ω | VIN=6V, VEN=0V | 5 | ||
| Junction-to-ambient Thermal Resistance, SOT23-3L | RθJA | 290 | ℃/W | Device mounted on FR-4 PCB, per JESD51-3 | 4 |
CAD (KiCad official)
- Symbol:
LW5228N23D - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files:
lw5228n23d-etched.step/lw5228n23d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lw5228n23d.step/lw5228n23d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (22 pp, sha256
554585e66fced619, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).