component
LW3112A23E
Public Made by Adomby adom
Lewa Micro Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LW3112A23E
Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5L
LW3112A23E from Lewa Micro, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input pin; use the recommended value or a larger ceramic capacitor from IN to ground, placed as close to the device as possible, with VIN supply range 1.8 V to 7.0 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin: drive above VEN(HI) (1.5 V typ./max per electrical table) to turn on the regulator, and below VEN(LO) (0.5 V) to put the LDO into shutdown mode. |
| 4 | NC | unconnected | No internal connection; ground this pin for better thermal performance. |
| 5 | VOUT | power_out | Regulated output voltage pin; connect a low-ESR capacitor of the nominal recommended value or larger from OUT to GND, and an internal pulldown discharges OUT when the regulator is in shutdown. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 1.8 | 7 | V | 5 | ||
| Output Accuracy | VOUT | -1 | 1 | % | IOUT= 1mA | 5 | |
| Quiescent Current | IQ | 40 | 60 | μA | VIN= VEN= VOUT +1V, No Load | 5 | |
| Current Limit | ILIM | 520 | 700 | mA | 5 | ||
| Shutdown Current | ISHD | 0.1 | μA | VIN=7.0V, VEN=0V | 5 | ||
| Short Current | ISHORT | 100 | mA | VOUT=0V | 5 | ||
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | 0.05 | 0.15 | %/V | VIN= VOUT +1.0V to 7.0V, IOUT=1mA | 5 | |
| Load Regulation | ΔVOUT | 30 | 60 | mV | 1mA≤IOUT≤500mA | 5 | |
| EN High Voltage | VENH | 1.5 | V | VIN=1.8V to 7.0V, IOUT=1mA | 5 | ||
| EN Low Voltage | VENL | 0.5 | V | 5 | |||
| Absolute Max Input Voltage | VIN | -0.3 | 8 | V | 4 | ||
| Absolute Max EN Pin Voltage | VEN | -0.3 | 8 | V | 4 | ||
| Absolute Max VOUT Pin Voltage | VOUT | -0.3 | V | Upper limit printed as (VIN+0.3) | 4 | ||
| ESD Susceptibility HBM | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Absolute Max Junction Temperature | TJ | -40 | 150 | ℃ | 4 | ||
| Storage Temperature Range | TSTG | -40 | 150 | ℃ | 4 | ||
| Lead Temperature (Soldering) | TSOLDER | 260 | ℃ | 10 s | 4 | ||
| Recommended VIN Supply Voltage | VIN | 1.8 | 7 | V | 4 | ||
| Recommended EN Pin Voltage | VEN | 0 | 7 | V | 4 | ||
| Recommended VOUT Pin Voltage | VOUT | 1.2 | 5 | V | 4 | ||
| Recommended Output Current | IOUT | 0 | 500 | mA | 4 | ||
| Recommended Junction Temperature Range | TJ | -40 | 125 | ℃ | 4 | ||
| Junction-to-ambient Thermal Resistance SOT23-5L | RθJA | 390 | ℃/W | SOT23-5L package, device mounted on FR-4 PCB per JESD51-3 | 4 | ||
| Startup Time | TSTR | 60 | μs | From VEN L→H to 95%*VOUT, COUT=1μF, No Load | 5 | ||
| Power Supply Rejection Ratio f=217Hz | PSRR | 77 | dB | VIN= 4.3V, VOUT=3.3V, VPP=0.5V, IOUT=10mA, f=217Hz | 5 | ||
| Power Supply Rejection Ratio f=1kHz | PSRR | 80 | dB | VIN= 4.3V, VOUT=3.3V, VPP=0.5V, IOUT=10mA, f=1kHz | 5 | ||
| Power Supply Rejection Ratio f=10kHz | PSRR | 67 | dB | VIN= 4.3V, VOUT=3.3V, VPP=0.5V, IOUT=10mA, f=10kHz | 5 | ||
| Output Voltage Noise IOUT=0mA | en | 92 | μVRMS | VIN= 4.3V, VOUT=3.3V, f=10Hz to 100kHz, IOUT=0mA | 5 | ||
| Output Voltage Noise IOUT=10mA | en | 102 | μVRMS | VIN= 4.3V, VOUT=3.3V, f=10Hz to 100kHz, IOUT=10mA | 5 | ||
| Thermal Shutdown Temperature | TSD | 155 | ℃ | Temperature rising | 5 | ||
| TSD Hysteresis | △TSD | 20 | ℃ | Temperature falling | 5 | ||
| Output Discharge Resistance | RDSCHG | 65 | Ω | VIN= 7.0V, VEN=0V | 5 |
CAD (KiCad official)
- Symbol:
LW3112A23E - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
lw3112a23e-etched.step/lw3112a23e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lw3112a23e.step/lw3112a23e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (25 pp, sha256
56df88266c01136c, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LW3112A23E
**Lewa Micro** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5L
LW3112A23E from Lewa Micro, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input pin; use the recommended value or a larger ceramic capacitor from IN to ground, placed as close to the device as possible, with VIN supply range 1.8 V to 7.0 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable pin: drive above VEN(HI) (1.5 V typ./max per electrical table) to turn on the regulator, and below VEN(LO) (0.5 V) to put the LDO into shutdown mode. |
| 4 | NC | unconnected | No internal connection; ground this pin for better thermal performance. |
| 5 | VOUT | power_out | Regulated output voltage pin; connect a low-ESR capacitor of the nominal recommended value or larger from OUT to GND, and an internal pulldown discharges OUT when the regulator is in shutdown. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 1.8 | | 7 | V | | 5 |
| Output Accuracy | VOUT | -1 | | 1 | % | IOUT= 1mA | 5 |
| Quiescent Current | IQ | | 40 | 60 | μA | VIN= VEN= VOUT +1V, No Load | 5 |
| Current Limit | ILIM | | 520 | 700 | mA | | 5 |
| Shutdown Current | ISHD | | | 0.1 | μA | VIN=7.0V, VEN=0V | 5 |
| Short Current | ISHORT | | | 100 | mA | VOUT=0V | 5 |
| Line Regulation | ΔVOUT/(ΔVIN*VOUT(NOM)) | | 0.05 | 0.15 | %/V | VIN= VOUT +1.0V to 7.0V, IOUT=1mA | 5 |
| Load Regulation | ΔVOUT | | 30 | 60 | mV | 1mA≤IOUT≤500mA | 5 |
| EN High Voltage | VENH | 1.5 | | | V | VIN=1.8V to 7.0V, IOUT=1mA | 5 |
| EN Low Voltage | VENL | | | 0.5 | V | | 5 |
| Absolute Max Input Voltage | VIN | -0.3 | | 8 | V | | 4 |
| Absolute Max EN Pin Voltage | VEN | -0.3 | | 8 | V | | 4 |
| Absolute Max VOUT Pin Voltage | VOUT | -0.3 | | | V | Upper limit printed as (VIN+0.3) | 4 |
| ESD Susceptibility HBM | V(ESD) | -2000 | | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 4 |
| Absolute Max Junction Temperature | TJ | -40 | | 150 | ℃ | | 4 |
| Storage Temperature Range | TSTG | -40 | | 150 | ℃ | | 4 |
| Lead Temperature (Soldering) | TSOLDER | | | 260 | ℃ | 10 s | 4 |
| Recommended VIN Supply Voltage | VIN | 1.8 | | 7 | V | | 4 |
| Recommended EN Pin Voltage | VEN | 0 | | 7 | V | | 4 |
| Recommended VOUT Pin Voltage | VOUT | 1.2 | | 5 | V | | 4 |
| Recommended Output Current | IOUT | 0 | | 500 | mA | | 4 |
| Recommended Junction Temperature Range | TJ | -40 | | 125 | ℃ | | 4 |
| Junction-to-ambient Thermal Resistance SOT23-5L | RθJA | | 390 | | ℃/W | SOT23-5L package, device mounted on FR-4 PCB per JESD51-3 | 4 |
| Startup Time | TSTR | | 60 | | μs | From VEN L→H to 95%*VOUT, COUT=1μF, No Load | 5 |
| Power Supply Rejection Ratio f=217Hz | PSRR | | 77 | | dB | VIN= 4.3V, VOUT=3.3V, VPP=0.5V, IOUT=10mA, f=217Hz | 5 |
| Power Supply Rejection Ratio f=1kHz | PSRR | | 80 | | dB | VIN= 4.3V, VOUT=3.3V, VPP=0.5V, IOUT=10mA, f=1kHz | 5 |
| Power Supply Rejection Ratio f=10kHz | PSRR | | 67 | | dB | VIN= 4.3V, VOUT=3.3V, VPP=0.5V, IOUT=10mA, f=10kHz | 5 |
| Output Voltage Noise IOUT=0mA | en | | 92 | | μVRMS | VIN= 4.3V, VOUT=3.3V, f=10Hz to 100kHz, IOUT=0mA | 5 |
| Output Voltage Noise IOUT=10mA | en | | 102 | | μVRMS | VIN= 4.3V, VOUT=3.3V, f=10Hz to 100kHz, IOUT=10mA | 5 |
| Thermal Shutdown Temperature | TSD | | 155 | | ℃ | Temperature rising | 5 |
| TSD Hysteresis | △TSD | | 20 | | ℃ | Temperature falling | 5 |
| Output Discharge Resistance | RDSCHG | | 65 | | Ω | VIN= 7.0V, VEN=0V | 5 |
## CAD (KiCad official)
- Symbol: `LW3112A23E`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `lw3112a23e-etched.step` / `lw3112a23e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lw3112a23e.step` / `lw3112a23e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Lewa Micro datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758012212143370240) (25 pp, sha256 `56df88266c01136c`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lw3112a23e-datasheet.pdf)