component

LV8968BBUWR2G

Public Made by Adom

by adom

onsemi Motor Driver ICs, TQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icslv8968bbuwr2gfactory-2.0.0extractor-text

Verified LV8968BBUWR2G

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LV8968BBUWR2G · TQFP-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 35-page datasheet
  • ✓distributor: lcsc C603211, digikey LV8968BBUWR2GOSTR-ND, mouser 863-LV8968BBUWR2G
  • ✓family: TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0mrcl31r/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lv8968bbuwr2g.kicad_sym✓ lv8968bbuwr2g.kicad_mod✓ lv8968bbuwr2g.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers lv8968bbuwr2g: viewers · Ray 5d ago
lv8968bbuwr2g-etched.glb Publish 0.1.0 · Ray 5d ago
lv8968bbuwr2g-etched.step lv8968bbuwr2g: factory component page (tier=mfr) · Ray 5d ago
lv8968bbuwr2g-hero.glb lv8968bbuwr2g: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
lv8968bbuwr2g-hero.overlay.json Publish 0.1.0 · Ray 5d ago
lv8968bbuwr2g.glb Publish 0.1.0 · Ray 5d ago
lv8968bbuwr2g.kicad_mod Publish 0.1.0 · Ray 5d ago
lv8968bbuwr2g.kicad_sym Publish 0.1.0 · Ray 5d ago
lv8968bbuwr2g.lbr Publish 0.1.0 · Ray 5d ago
lv8968bbuwr2g.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 49 pins · Ray 5d ago

LV8968BBUWR2G

onsemi · Motor Driver ICs · TQFP-48-EP(7x7)

LV8968BBUWR2G from onsemi, in a TQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_out 5 V or 3.3 V linear regulator output selected by SPI register setting, can provide up to 50 mA.
2 IH1 input Active high digital control input to activate GH1.
3 IL1 input Active low digital control input to activate GL1.
4 IH2 input Active high digital control input to activate GH2.
5 IL2 input Active low digital control input to activate GL2.
6 IH3 input Active high digital control input to activate GH3.
7 IL3 input Active low digital control input to activate GL3.
8 VMCRES output Open drain reset output for the microcontroller that goes low for VCC under-voltage fault, and optionally for watchdog reset and thermal shutdown.
9 DIAG output Open drain error or diagnostic output connected to the microcontroller interrupt line, functionality defined by internal register settings.
10 RXD output Open drain PWM data output to the microcontroller that follows the digital level of PWMIN.
11 NC unconnected No connection.
12 PWMIN input Input for battery level control signal whose digital level appears on RXD.
13 CSB input High voltage level translator; digital level is active low SPI interface chip selection pin.
14 SCLK input SPI interface clock input; SI data is latched on the rising edge.
15 SI input SPI interface serial data input pin.
16 SO output SPI interface serial data output; high level is pulled to VCC.
17 NC unconnected No connection.
18 AGND power_in Ground pin.
19 AOUT output Output for various internal analog signals selected via SPI register, scaled to 2 V full scale range.
20 ISO output Current sense amplifier output to connect to the microcontroller AD converter, full scale range 2 V.
21 ISN input Current sense amplifier minus input, connected to the GND side of the shunt resistor with Kelvin leads.
22 ISP input Current sense amplifier plus input, connected to the top side of the shunt resistor with Kelvin leads.
23 NC unconnected No connection.
24 SL3 passive Low side source connection of the power stage and return path for gate current of GL3.
25 GL3 output Gate driver output for low side FETs switching between VG and SL3; use at least 10 gate resistors to protect against current spikes.
26 SH3 bidirectional Connection for the motor phase terminal controlled by GH3 and GL3, return path for high-side drivers and input for back EMF sensing.
27 GH3 output Gate driver output for high side FETs switching between BS3 and SH3; use at least 10 gate resistors to protect against current spikes.
28 BS3 power_in Supply pin for high side driver GH3, needs a bootstrap capacitor to SH3 and a diode in reverse connection to VG.
29 SL2 passive Low side source connection of the power stage and return path for gate current of GL2.
30 GL2 output Gate driver output for low side FETs switching between VG and SL2; use at least 10 gate resistors to protect against current spikes.
31 SH2 bidirectional Connection for the motor phase terminal controlled by GH2 and GL2, return path for high-side drivers and input for back EMF sensing.
32 GH2 output Gate driver output for high side FETs switching between BS2 and SH2; use at least 10 gate resistors to protect against current spikes.
33 BS2 power_in Supply pin for high side driver GH2, needs a bootstrap capacitor to SH2 and a diode in reverse connection to VG.
34 SL1 passive Low side source connection of the power stage and return path for gate current of GL1.
35 GL1 output Gate driver output for low side FETs switching between VG and SL1; use at least 10 gate resistors to protect against current spikes.
36 SH1 bidirectional Connection for the motor phase terminal controlled by GH1 and GL1, return path for high-side drivers and input for back EMF sensing.
37 GH1 output Gate driver output for high side FETs switching between BS1 and SH1; use at least 10 gate resistors to protect against current spikes.
38 BS1 power_in Supply pin for high side driver GH1, needs a bootstrap capacitor to SH1 and a diode in reverse connection to VG.
39 VDH input Sense input for supply voltage and short circuit detection of high side power FETs, connected through a 100 resistor to the common drain of the power bridge.
40 VG power_in Power supply pin for low-side gate drive GL[1-3] directly and GH[1-3] through the bootstrap circuit, connect decoupling capacitor between VG and GND.
41 NC unconnected No connection.
42 VGIN power_in Gate supply input normally shorted to VS; insert a charge pump between VS and VGIN if low voltage operation is required.
43 VS power_in Power supply pin.
44 WAKE input WAKE up pin for internal power supply; H for operating mode, L or open for sleep mode.
45 NC unconnected No connection.
46 EN input Active high digital input that activates the outputs and can hold the IC operating when WAKE is low; a falling edge clears the error flags.
47 V3RO power_out Internal regulator output pin; connect capacitor between this pin and GND.
48 V3RI power_in Internal regulator feedback pin for control circuit and logic power supply, connect to V3RO and do not load beyond 1 mA.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer onsemi
Package TQFP-48-EP(7x7)
Category Power Management ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage -0.3 40 V Pins VS, VDH, VGIN 7
Gate Voltage to GND -0.3 40 V Pin VG 7
Bootstrap to GND -0.3 40 V Pins BS[1-3] 7
Bootstrap to SH -0.3 40 V Pins BS[1-3] to SH[1-3] 7
Logic Power Supply -0.3 3.6 V Pins V3RI, V3RO 7
5 V Regulator Voltage -0.3 5.5 V Pin VCC 7
VS Level Signal Voltage -0.3 40 V Pins WAKE, PWMIN 7
Digital Inputs -0.3 40 V Pins CSB, EN, SCLK, SI, IH[1-3], IL[1-3] 7
Open Drain Voltage -0.3 40 V Pins VMCRES, RXD, DIAG 7
Digital Output Voltage -0.3 V Pin SO; upper limit printed as VVCC+0.3 V 7
Current Sense Input -3 V Pins ISP, ISN; upper limit printed as VV3RI+0.3 V 7
Analog Output -0.3 V Pins ISO, AOUT; upper limit printed as VV3RO+0.3 V 7
High-side Output to GND -3 40 V Pins GH[1-3] 7
Motor Phase -3 40 V Pins SH[1-3] 7
Low-side Output to GND -3 40 V Pins GL[1-3] 7
Low-side Source Pin to GND -3 40 V Pins SL[1-3] 7
Voltage between HS Gate and Phase -0.3 20 V GH[n] to SH[n] for n = {1,2,3} 7
Storage Temperature -55 150 °C 7
Junction Temperature -40 150 °C 7
Junction Temperature (Note 1) 150 175 °C Note 1: operation above 150°C not guaranteed without written agreement 7
ESD Human Body Model 2 kV AEC Q100_002 7
ESD Charge Device Model 750 V AEC Q100_011 7
Allowable Power 2430 mW SQFP48K at 70°C 7
Thermal Resistance Junction-Ambient JA 33 °C/W JESD51-7 7
Thermal Resistance Junction-Case JC 2 °C/W 7
VS supply voltage range (normal mode) VSNO 8 12 28 V Normal mode (Note 2) 8
VS supply voltage range (logic level mode) VSLO 6 33 V Logic level mode 8
VS supply voltage range (full logic functionality) VSLOF 4.5 40 V Full logic functionality, driver stage off (t < 400 ms) (Note 3) 8
VS supply current standby ISTBY 7 11 16 mA Standby mode; VS & VGIN shorted; VS = 6 V to 25 V 8
VS supply current sleep ISLEEP 25 50 A Sleep mode at 25°C; VS & VGIN shorted 8
WAKE input voltage low level VTHWKL 0 1.3 V Low level 8
WAKE input voltage high level VTHWKH 2.7 V High level; upper limit printed as VS 8
WAKE pulldown resistor RPDWK 50 100 200 k 8
PWMIN switching level low VTHPIL 0 V Low level; upper limit printed as 0.4 × VS 8
PWMIN pulldown resistor RPDPI 50 100 200 k 8
PWMIN frequency range FPWMIN 0 30 kHz 8
V3RO output voltage V3RO 3.135 3.3 3.465 V 8
Output voltage 5V VC5RO 4.9 5 5.1 V REGSEL = 1, No load 8
Output voltage 3.3V VC3RO 3.23 3.3 3.37 V REGSEL = 0, No load 8
Load regulation VCCLR 80 mV Io = -5 mA to -50 mA 8
Output current limit VCCILIM 50 180 mA 8
Low-side Rdson to SL[1-3] RONLSSK 6 15 L level, Io = 10 mA 8
Low-side Rdson to SH[1-3] RONLSSC 12 22 H level, Io = -10 mA 8
High-side Rdson to SH[1-3] RONHSSK 6 15 L level, Io = 10 mA 8
High-side Rdson to BS[1-3] RONHSSC 12 22 H level, Io = -10 mA 8
Propagation delay ON difference GH and GL DPDON -20 20 nS 3 phase difference of GH1, GH2, GH3 and of GL1, GL2, GL3 8
Propagation delay OFF difference GH and GL DPDOFF -20 20 nS 3 phase difference of GH1, GH2, GH3 and of GL1, GL2, GL3 8
BS internal current IBSC 800 A 8
VG output voltage normal mode VGNO 7 11 12 V Normal mode, IVG < 40 mA 9
VG output voltage logic level mode VGLO 5 6 7 V Logic level mode 9
VG current limit VGILIM 40 180 mA 9
AOUT full scale range AOFLSCR 2.1 V 9
Reference voltage ISO (OCVR = 0) VRCSA0 1.425 1.5 1.575 V OCVR = 0, GAIN = 30, ISP = ISN = 0.2 V 9
Reference voltage ISO (OCVR = 1) VRCSA1 0.125 0.2 0.275 V OCVR = 1, GAIN = 30, ISP = ISN = 0.2 V 9
Gain OCGAIN = 00 CSAG00 6.53 7.5 8.63 OCGAIN = 00 9
Gain OCGAIN = 11 CSAG11 26 30 34.3 OCGAIN = 11 9
VS voltage warning over-voltage VSOVTH 16 17 18 V Over-voltage 9
VS voltage warning under-voltage VSUVTH 7 7.5 8 V Under-voltage 9
VDH voltage warning over-voltage VDHOVTH 25 26.5 28 V Over-voltage 9
VG under-voltage normal mode VGNUVTH 5 6 7 V Normal mode 9
VG under-voltage logic level mode VGLUVTH 3.5 4 4.5 V Logic level mode 9
VCC under-voltage REGSEL = 0 VC3UVTH 2.3 2.7 V REGSEL = 0 9
VCC under-voltage REGSEL = 1 VC5UVTH 3.8 4.2 V REGSEL = 1 9
FET short protection level FSDL0000 FSDL0000 75 100 125 mV FSDL = 0000 9
FET short protection level FSDL1111 FSDL1111 1280 1600 1920 mV FSDL = 1111 9
Thermal shutdown TSDT1 TSDT1 175 °C TSTS = 1 (Note 4) 10
Thermal shutdown TSDT0 TSDT0 150 °C TSTS = 0 (Note 4) 10
Thermal warning TWT1 TWT1 150 °C TSTS = 1 (Note 4) 10
Thermal warning TWT0 TWT0 125 °C TSTS = 0 (Note 4) 10
Watchdog closed window time WDCW 0.8 102.4 ms WDWT[2:0] typical values 10
SPI clock frequency FSPI 4.5 MHz 10

CAD (KiCad official)

  • Symbol: LV8968BBUWR2G
  • Footprint: Package_QFP:TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: lv8968bbuwr2g-etched.step / lv8968bbuwr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lv8968bbuwr2g.step / lv8968bbuwr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (35 pp, sha256 946b346c2b40807b, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF