# LV14360SDDAR

**Texas Instruments** · DC-DC Converters · SOIC-8-EP

LV14360SDDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap capacitor connection for the high-side MOSFET driver; connect a high-quality 0.1-µF capacitor from BOOT to SW. |
| 2 | VIN | power_in | Input supply pin with a recommended operating range of 4.3 V to 60 V; connect to the power supply and bypass capacitor CIN, keeping the path from VIN to CIN and GND as short as possible. |
| 3 | EN | input | Precision enable input with internal pullup current source; pull below 1.2 V to disable, float or connect to VIN to enable, and it is rated 0 V to 60 V. |
| 4 | RT/SYNC | input | Resistor timing or external clock input that sets the switching frequency (200 kHz to 2 MHz in RT mode, 250 kHz to 2 MHz in SYNC mode) and is rated 0 V to 3.3 V. |
| 5 | FB | input | Feedback input connected to the feedback divider to set VOUT; it must not be shorted to ground during operation and is rated 0 V to 5 V. |
| 6 | SS | input | Soft-start pin for the soft-start version, connected to a capacitor that sets the soft-start time; it is rated 0 V to 3 V. |
| 7 | GND | power_in | System ground pin. |
| 8 | SW | power_out | Switching output of the regulator, internally connected to the high-side power MOSFET and connected to the power inductor; rated -1 V to 60 V. |
| 9 | Thermal Pad | power_in | Major heat dissipation path of the die that must be connected to the ground plane on the PCB. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, EN to GND |  | -0.3 |  | 65 | V |  | 4 |
| BOOT to GND |  | -0.3 |  | 71 | V |  | 4 |
| SS to GND |  | -0.3 |  | 5 | V |  | 4 |
| FB to GND |  | -0.3 |  | 7 | V |  | 4 |
| RT/SYNC to GND |  | -0.3 |  | 3.6 | V |  | 4 |
| BOOT to SW |  |  |  | 6.5 | V |  | 4 |
| SW to GND |  | -3 |  | 65 | V |  | 4 |
| Junction temperature, TJ | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature, Tstg | Tstg | -65 |  | 150 | °C |  | 4 |
| VIN | VIN | 4.3 |  | 60 | V |  | 4 |
| VOUT | VOUT | 0.8 |  | 50 | V |  | 4 |
| SW |  | -1 |  | 60 | V |  | 4 |
| FB |  | 0 |  | 5 | V |  | 4 |
| EN |  | 0 |  | 60 | V |  | 4 |
| RT/SYNC |  | 0 |  | 3.3 | V |  | 4 |
| SS |  | 0 |  | 3 | V |  | 4 |
| Operating junction temperature, TJ | TJ | -40 |  | 125 | °C |  | 4 |
| Switching frequency range at RT mode |  | 200 |  | 2000 | kHz |  | 4 |
| Switching frequency range at SYNC mode |  | 250 |  | 2000 | kHz |  | 4 |
| VIN Operation input voltage | VIN | 4.3 |  | 60 | V |  | 5 |
| Under voltage lockout thresholds |  | 3.8 | 4 | 4.2 | V | Rising threshold | 5 |
| ISHDN Shutdown supply current | ISHDN |  | 1 | 3 | μA | VEN = 0 V, TA = 25°C, 4.3 V ≤ VIN ≤ 60 V | 5 |
| EN Threshold Voltage | VEN_TH | 1.05 | 1.2 | 1.38 | V |  | 5 |
| Feedback voltage | VFB | 0.746 | 0.75 | 0.754 | V | TJ = 25°C | 6 |
| Feedback voltage | VFB | 0.735 | 0.75 | 0.765 | V | TJ = –40°C to 125°C | 6 |
| On-resistance (high-side MOSFET) | RDS_ON |  | 155 | 320 | mΩ | VIN = 12 V, BOOT to SW = 5.8 V | 6 |
| Current limit (high-side MOSFET) | ILIMT | 3.8 | 4.75 | 5.7 | A | VIN = 12 V, TA = 25°C, Open Loop | 6 |
| SYNC clock high level threshold | VSYNC_HI | 1.7 |  |  | V |  | 6 |
| SYNC clock low level threshold | VSYNC_LO |  |  | 0.5 | V |  | 6 |
| Minimum SYNC input pulse width | TSYNC_MIN | 30 |  |  | ns | Measured at 500 kHz, VSYNC_HI > 3 V, VSYNC_LO < 0.3 V | 6 |
| Switching frequency range at SYNC mode |  | 250 |  | 2000 | kHz | SYNC mode | 6 |
| RθJA Junction-to-ambient thermal resistance | RθJA |  | 42.5 |  | °C/W |  | 5 |
| ψJT Junction-to-top characterization parameter | ψJT |  | 9.9 |  | °C/W |  | 5 |
| ψJB Junction-to-board characterization parameter | ψJB |  | 25.4 |  | °C/W |  | 5 |
| RθJC(top) Junction-to-case (top) thermal resistance | RθJC(top) |  | 56.1 |  | °C/W |  | 5 |
| RθJC(bot) Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 3.8 |  | °C/W |  | 5 |
| RθJB Junction-to-board thermal resistance | RθJB |  | 25.5 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `LV14360SDDAR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `lv14360sddar-etched.step` / `lv14360sddar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lv14360sddar.step` / `lv14360sddar.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lv14360) (35 pp, sha256 `8e75b5bff257117f`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lv14360sddar-datasheet.pdf)