component
LTP3118XT5
Public Made by Adomby adom
Linearin Linear Voltage Regulators (LDO), SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 4h ago |
| viewers | 4h ago |
| ltp3118xt5-etched.glb | 4h ago |
| ltp3118xt5-etched.step | 4h ago |
| ltp3118xt5-hero.glb | 4h ago |
| ltp3118xt5-hero.overlay.json | 4h ago |
| ltp3118xt5.glb | 4h ago |
| ltp3118xt5.kicad_mod | 4h ago |
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| ltp3118xt5.lbr | 4h ago |
| ltp3118xt5.step | 4h ago |
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LTP3118XT5
Linearin · Linear Voltage Regulators (LDO) · SOT-23-5L
LTP3118XT5 from Linearin, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Supply input pin that must be closely decoupled to GND with a 1μF or greater ceramic capacitor. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable control input, active high; do not leave EN floating. |
| 4 | NC | unconnected | No connection. |
| 5 | OUT | power_out | Output pin; bypass with a 1μF ceramic capacitor from this pin to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin |
| Package | SOT-23-5L |
| Category | Power Management ICs |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 1.9 | 5.5 | V | 6 | ||
| Load Current | ILOAD | 0 | 300 | mA | 6 | ||
| Output Voltage Tolerance | ΔVOUT | -2 | 2 | %VOUT | VIN = 2.8 V to 5.5 V, IOUT = 1 mA to 300mA | 6 | |
| IN Voltage | VIN | -0.3 | 6 | V | 5 | ||
| Other Pin Voltage | -0.3 | V | Maximum printed as VIN + 0.3 V | 5 | |||
| Operating Junction Temperature | TOP | -40 | 125 | °C | 5 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 5 | ||
| Lead Temperature (Soldering, 10 sec) | TL | 300 | °C | Soldering, 10 sec | 5 | ||
| Input Shutdown Quiescent Current | ISHDN | 0.2 | 1 | μA | Disabled, VEN = 0 V | 6 | |
| Input Quiescent Current | IQ | 14 | 25 | μA | VIN > 1.9 V, VEN > 1.2 V, IOUT = 0 mA | 6 | |
| Standby Current | Istandby | 0.2 | 1 | μA | VEN = 0 V | 6 | |
| Dropout Voltage | VDROP | 50 | 100 | mV | IOUT = 100 mA | 6 | |
| Dropout Voltage | VDROP | 180 | 300 | mV | IOUT = 300 mA | 6 | |
| Short Circuit Current Limit | ILMT | 300 | 500 | mA | TA = 25°C | 6 | |
| Output Discharge FET RDSON | RDischrg | 20 | 30 | 40 | Ω | VEN < VIL (output disable) | 6 |
| EN Input Logic Low Voltage | VIL | 0.4 | V | VIN = 1.8 V to 5.5 V, VEN falling until the output is disabled | 6 | ||
| EN Input Logic High Voltage | VIH | 1 | V | VIN = 1.8 V to 5.5 V, VEN rising until the output is enabled | 6 | ||
| EN Input leakage current | IEN | 0.01 | 1 | μA | VIN = 5.5 V, VEN = 0 V | 6 | |
| EN Input leakage current | IEN | 5.5 | μA | VIN = 5.5 V, VEN = 5.5 V | 6 | ||
| Thermal shutdown threshold | TSHDN | 155 | °C | VIN = 2.8 V, TJ rising | 6 | ||
| Thermal shutdown hysteresis | THYS | 15 | °C | VIN = 2.8 V, TJ falling from shutdown | 6 | ||
| Output Turn-on Delay Time | TD(ON) | 150 | 250 | μs | From VEN > VIH to VOUT = 95% of VOUT(NOM) | 6 | |
| Line Regulation | 0.02 | %mA | VIN = 2.8 V to 5.5 V, IOUT = 1 mA | 6 | |||
| Load Regulation | 0.001 | %mA | IOUT = 1 mA to 300 mA | 6 | |||
| Line transient | ΔVOUT | 10 | mV | VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 1.6V) in 10 μs | 7 | ||
| Load transient | ΔVOUT | 20 | mV | IOUT = 1 mA to 300 mA in 10 μs | 7 | ||
| Overshoot on start-up | Overshoot | 5 | % | Stated as percentage of VOUT(NOM) | 7 | ||
| Power Supply Rejection Ratio | PSRR | 94 | dB | f = 100 Hz, IOUT = 1 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 90 | dB | f = 1 kHz, IOUT = 1 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 84 | dB | f = 10 kHz, IOUT = 1 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 71 | dB | f = 100 kHz, IOUT = 1 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 60 | dB | f = 1 MHz, IOUT = 1 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 83 | dB | f = 1 kHz, IOUT = 20 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 77 | dB | f = 10 kHz, IOUT = 20 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 58 | dB | f = 1 MHz, IOUT = 20 mA | 6 | ||
| Output Noise Voltage | eN | 10 | μVRMS | BW = 10 Hz to 100 kHz, IOUT = 1 mA | 6 | ||
| Output Noise Voltage | eN | 6.5 | μVRMS | BW = 10 Hz to 100 kHz, IOUT = 300 mA | 6 |
CAD (KiCad official)
- Symbol:
LTP3118XT5 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files:
ltp3118xt5-etched.step/ltp3118xt5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltp3118xt5.step/ltp3118xt5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Linearin datasheet (11 pp, sha256
e484f4718e68c60c, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).