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LTM4625IY#PBF

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Analog Devices DC-DC Converters, BGA-25. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LTM4625IY#PBF

Analog Devices · DC-DC Converters · BGA-25

LTM4625IY#PBF from Analog Devices, in a BGA-25. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 COMP output Current control threshold and error amplifier compensation point, with a normal range of 0.3V to 1.8V; it is strictly an output and must not be driven.
A2 TRACK/SS input Output tracking and soft-start input: a voltage below 0.6V overrides the internal reference and servos FB to the TRACK/SS voltage, and an internal 2µA pull-up from INTVCC lets a capacitor set the soft-start.
A3 RUN input Run control input that enables the regulator when raised above 1.2V and shuts it down when pulled below 1.1V; it must not be left floating.
A4 FREQ passive Sets the switching frequency, internally 1MHz, with an external resistor to SGND to increase frequency or to INTVCC to reduce it; the programmable range is 800kHz to 4MHz.
A5 CLKIN input External synchronization input to the phase detector, internally terminated to SGND with 20k; clock high must be above 2V and clock low below 0.3V.
B1 FB input Negative input of the error amplifier, internally connected to VOUT through a 60.4k precision resistor, with an external resistor to SGND programming other output voltages.
B2 PHMODE input Phase selector control: tie to INTVCC for 2-phase, SGND for 3-phase, or INTVCC/2 for 4-phase operation.
B3 GND power_in Power ground pin for both input and output returns.
B4 SGND power_in Signal ground connection, to be tied to GND with minimum distance.
B5 CLKOUT output Output clock for PolyPhase operation with peak-to-peak amplitude from INTVCC to GND; it must not be driven.
C1 VOUT power_out Power output pin; the load is applied between VOUT and GND, with output decoupling recommended directly between these pins and GND.
C2 PGOOD output Open-drain power-good output that is pulled to ground when the FB voltage is not within ±10% of the internal 0.6V reference.
C3 GND power_in Power ground pin for both input and output returns.
C4 MODE input Operation mode select: tie to INTVCC to force continuous synchronous operation, or to SGND to enable discontinuous mode at light loads; it must not be left floating.
C5 SVIN power_in Filtered input to the on-chip 3.3V regulator, normally tied to VIN or driven from an external supply of at least 4V that must also be greater than VOUT.
D1 VOUT power_out Power output pin; the load is applied between VOUT and GND, with output decoupling recommended directly between these pins and GND.
D2 VOUT power_out Power output pin; the load is applied between VOUT and GND, with output decoupling recommended directly between these pins and GND.
D3 GND power_in Power ground pin for both input and output returns.
D4 GND power_in Power ground pin for both input and output returns.
D5 VIN power_in Power input pin; apply the input voltage between VIN and GND, with input decoupling recommended directly between VIN and GND, within the 4V to 20V input range.
E1 VOUT power_out Power output pin; the load is applied between VOUT and GND, with output decoupling recommended directly between these pins and GND.
E2 VOUT power_out Power output pin; the load is applied between VOUT and GND, with output decoupling recommended directly between these pins and GND.
E3 GND power_in Power ground pin for both input and output returns.
E4 INTVCC power_out Internal regulator output that powers the internal drivers and control circuits; it is decoupled to GND with a 1µF low-ESR ceramic capacitor and must not be driven.
E5 VIN power_in Power input pin; apply the input voltage between VIN and GND, with input decoupling recommended directly between VIN and GND, within the 4V to 20V input range.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package BGA-25
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input DC Voltage (SVIN = VIN) VIN 4 20 V SVIN = VIN 2
Output Voltage Range VOUT 0.6 5.5 V 2
Output Voltage, Total Variation with Line and Load VOUT(DC) 1.477 1.5 1.523 V CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k, MODE = INTVCC, IOUT = 0A to 5A (Note 3), -40°C to 125°C 2
RUN Pin On Threshold VRUN 1.1 1.2 1.3 V VRUN Rising 2
Output Continuous Current Range IOUT(DC) 0 5 A VIN = 12V, VOUT = 1.5V 3
Line Regulation Accuracy ΔVOUT(Line)/VOUT 0.04 0.15 %/V VOUT = 1.5V, VIN = 4V to 20V, IOUT = 0A 3
Load Regulation Accuracy ΔVOUT (Load)/VOUT 0.5 1.5 % VOUT = 1.5V, IOUT = 0A to 5A 3
Voltage at FB Pin VFB 0.593 0.6 0.607 V IOUT = 0A, VOUT = 1.5V, -40°C to 125°C 3
Current at FB Pin IFB -30 30 nA (Note 4) 3
Resistor Between VOUT and FB Pins RFBHI 60.05 60.4 60.75 kΩ Resistor between VOUT and FB pins 3
PGOOD Trip Level, VFB Ramping Negative VPGOOD -15 -10 -7 % VFB With Respect to Set Output, VFB Ramping Negative 3
PGOOD Trip Level, VFB Ramping Positive VPGOOD 7 10 15 % VFB With Respect to Set Output, VFB Ramping Positive 3
PGOOD Voltage Low VPGL 0.02 0.1 V IPGOOD = 1mA 3
Internal VCC Voltage VINTVCC 3.1 3.2 3.3 V SVIN = 4V to 20V 3
VIN Undervoltage Lockout VIN(UVLO) 2.4 2.6 2.8 V VIN Falling 3
VIN, SVIN Absolute Maximum Voltage VIN, SVIN -0.3 22 V 2
RUN Absolute Maximum Voltage RUN -0.3 22 V 2
PGOOD, MODE, TRACK/SS, FREQ, PHMODE, CLKIN Absolute Maximum Voltage -0.3 V Upper limit printed as INTVCC 2
Internal Operating Temperature Range TJ -40 125 °C Notes 2, 5 2
Storage Temperature Range TSTG -65 150 °C 2
Peak Solder Reflow Body Temperature 245 °C Note 1 2
Operating Temperature Range, LTM4625I grade TJ -40 125 °C Internal operating temperature range (Note 2), LTM4625I 2
Maximum Junction Temperature TJMAX 125 °C 2
Thermal Resistance, Junction to Case (Top) θJCtop 17 °C/W JESD 51-12 2
Thermal Resistance, Junction to Case (Bottom) θJCbottom 11 °C/W JESD 51-12 2
Thermal Resistance, Junction to Board plus Board to Ambient θJB + θBA 22 °C/W JESD 51-12 2
Thermal Resistance, Junction to Ambient θJA 22 °C/W Derived from 95mm × 76mm PCB with 4 layers, JESD 51-12 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper • Use a separated SGND ground copper area for com￾ponents connected to signal pins. Connect the SGND 20

CAD (KiCad official)

  • Symbol: LTM4625IY#PBF
  • Footprint: Package_BGA:BGA-25_6.35x6.35mm_Layout5x5_P1.27mm
  • 3D model: BGA-25 (KiCad packages3D, STEP)
  • 3D model files: ltm4625iy-pbf-etched.step / ltm4625iy-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltm4625iy-pbf.step / ltm4625iy-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (26 pp, sha256 85df67ba0803249b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF