LTM4625EY#PBF from Analog Devices, in a BGA-25. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
A1	COMP	output	Current control threshold and error amplifier compensation point with normal range 0.3V to 1.8V; internally compensated, strictly an output, do not drive; tie COMP pins together for parallel operation.
A2	TRACK/SS	input	Output tracking and soft-start input; a voltage below 0.6V servos FB to TRACK/SS, and an internal 2µA pull-up from INTVCC allows a capacitor to set soft-start.
A3	RUN	input	Run control input that enables the regulator above 1.2V and shuts it down below 1.1V; do not leave floating (absolute max 22V).
A4	FREQ	input	Frequency set internally to 1MHz; a resistor to SGND increases frequency or a resistor to INTVCC reduces it.
A5	CLKIN	input	External synchronization input to the phase detector, internally terminated to SGND with 20k; PLL locks top NMOS turn-on to the CLKIN rising edge.
B1	FB	input	Negative input of the error amplifier, internally connected to VOUT through a 60.4k resistor; add a resistor to SGND to program output voltage, and tie FB pins together for parallel operation.
B2	PHMODE	input	Phase selector control input: tie to INTVCC for 2-phase, SGND for 3-phase, INTVCC/2 for 4-phase operation.
B3	GND	power_in	Power ground for both input and output returns.
B4	SGND	power_in	Signal ground connection; tie to GND with minimum distance and connect FREQ resistor, COMP component, MODE, TRACK/SS component and FB resistor to it as needed.
B5	CLKOUT	output	Output clock signal for PolyPhase operation with peak-to-peak amplitude INTVCC to GND, phase relative to CLKIN set by PHMODE; do not drive.
C1	VOUT	power_out	Power output pin; apply the load between VOUT and GND pins with output decoupling capacitance directly between them.
C2	PGOOD	output	Open-drain power good output pulled to ground when FB is not within ±10% of the internal 0.6V reference.
C3	GND	power_in	Power ground for both input and output returns.
C4	MODE	input	Operation mode select: tie to INTVCC for forced continuous operation, or to SGND for discontinuous mode at light loads; do not leave floating.
C5	SVIN	power_in	Signal VIN, filtered input to the on-chip 3.3V regulator; tie to VIN or to an external supply of at least 4V that must exceed VOUT (absolute max 22V).
D1	VOUT	power_out	Power output pin; apply the load between VOUT and GND pins with output decoupling capacitance directly between them.
D2	VOUT	power_out	Power output pin; apply the load between VOUT and GND pins with output decoupling capacitance directly between them.
D3	GND	power_in	Power ground for both input and output returns.
D4	GND	power_in	Power ground for both input and output returns.
D5	VIN	power_in	Power input pin; apply input voltage (4V to 20V, absolute max 22V) between VIN and GND pins with input decoupling capacitance directly between them.
E1	VOUT	power_out	Power output pin; apply the load between VOUT and GND pins with output decoupling capacitance directly between them.
E2	VOUT	power_out	Power output pin; apply the load between VOUT and GND pins with output decoupling capacitance directly between them.
E3	GND	power_in	Power ground for both input and output returns.
E4	INTVCC	power_out	Internal regulator output (3.1V to 3.3V) powering the internal drivers and control circuits, internally decoupled with 1µF to GND; do not drive.
E5	VIN	power_in	Power input pin; apply input voltage (4V to 20V, absolute max 22V) between VIN and GND pins with input decoupling capacitance directly between them.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	BGA-25
Category	Power Management ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input DC Voltage	VIN	4		20	V	SVIN = VIN	2
Output Voltage Range	VOUT	0.6		5.5	V		2
Output Voltage, Total Variation with Line and Load	VOUT(DC)	1.477	1.5	1.523	V	CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k, MODE = INTVCC, IOUT = 0A to 5A, -40°C to 125°C	2
RUN Pin On Threshold	VRUN	1.1	1.2	1.3	V	VRUN Rising	2
Input Supply Bias Current (MODE = INTVCC)	IQ(SVIN)		6		mA	VIN = 12V, VOUT = 1.5V, MODE = INTVCC	2
Input Supply Bias Current (MODE = GND)	IQ(SVIN)		2		mA	VIN = 12V, VOUT = 1.5V, MODE = GND	2
Input Supply Bias Current (Shutdown)	IQ(SVIN)		11		µA	Shutdown, RUN = 0, VIN = 12V	2
Input Supply Current	IS(VIN)		0.75		A	VIN = 12V, VOUT = 1.5V, IOUT = 5A	2
Output Continuous Current Range	IOUT(DC)	0		5	A	VIN = 12V, VOUT = 1.5V	3
Line Regulation Accuracy	ΔVOUT(Line)/VOUT		0.04	0.15	%/V	VOUT = 1.5V, VIN = 4V to 20V, IOUT = 0A	3
Load Regulation Accuracy	ΔVOUT(Load)/VOUT		0.5	1.5	%	VOUT = 1.5V, IOUT = 0A to 5A	3
Output Current Limit	IOUTPK	6		7	A	VIN = 12V, VOUT = 1.5V	3
Voltage at FB Pin	VFB	0.593	0.6	0.607	V	IOUT = 0A, VOUT = 1.5V, -40°C to 125°C	3
Resistor Between VOUT and FB Pins	RFBHI	60.05	60.4	60.75	kΩ		3
Current at FB Pin	IFB	-30		30	nA	Note 4	3
Track Pin Soft-Start Pull-Up Current	ITRACK/SS		2	4	µA	TRACK/SS = 0V	3
VIN Undervoltage Lockout	VIN(UVLO)	2.4	2.6	2.8	V	VIN Falling	3
VIN UVLO Hysteresis	VIN(UVLO)		350		mV	VIN Hysteresis	3
PGOOD Trip Level (Negative)	VPGOOD	-15	-10	-7	%	VFB With Respect to Set Output, VFB Ramping Negative	3
PGOOD Trip Level (Positive)	VPGOOD	7	10	15	%	VFB With Respect to Set Output, VFB Ramping Positive	3
PGOOD Leakage	IPGOOD			2	µA		3
PGOOD Voltage Low	VPGL		0.02	0.1	V	IPGOOD = 1mA	3
Internal VCC Voltage	VINTVCC	3.1	3.2	3.3	V	SVIN = 4V to 20V	3
Output Ripple Voltage	VOUT(AC)		5		mV	IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VOUT = 1.5V	3
Turn-On Overshoot	ΔVOUT(START)		30		mV	IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VOUT = 1.5V	3
Turn-On Time	tSTART		2.5		ms	COUT = 100µF Ceramic, No Load, TRACK/SS = 0.01µF, VIN = 12V, VOUT = 1.5V	3
Peak Deviation for Dynamic Load	ΔVOUTLS		160		mV	Load: 0% to 50% to 0% of Full Load, COUT = 47µF Ceramic, VIN = 12V, VOUT = 1.5V	3
Settling Time for Dynamic Load Step	tSETTLE		40		µs	Load: 0% to 50% to 0% of Full Load, COUT = 47µF Ceramic, VIN = 12V, VOUT = 1.5V	3
Minimum On-Time	tON(MIN)		40		ns	Note 4	3
Minimum Off-Time	tOFF(MIN)		70		ns	Note 4	3
Oscillator Frequency	fOSC		1		MHz		3
VIN, SVIN Voltage	VIN, SVIN	-0.3		22	V		2
RUN Voltage	RUN	-0.3		22	V		2
PGOOD, MODE, TRACK/SS, FREQ, PHMODE, CLKIN Voltage		-0.3		3.3	V	-0.3V to INTVCC (INTVCC is 3.3V max per VINTVCC)	2
Internal Operating Temperature Range		-40		125	°C	Notes 2, 5	2
Storage Temperature Range		-65		150	°C		2
Peak Solder Reflow Body Temperature				245	°C		2
Maximum Junction Temperature	TJMAX			125	°C		2
Thermal Resistance Junction-to-Case (Top)	θJCtop		17		°C/W	JESD51-12	2
Thermal Resistance Junction-to-Case (Bottom)	θJCbottom		11		°C/W	JESD51-12	2
Thermal Resistance Junction-to-Board plus Board-to-Ambient	θJB + θBA		22		°C/W	JESD51-12	2
Thermal Resistance Junction-to-Ambient	θJA		22		°C/W	Derived from 95mm × 76mm PCB with 4 layers	2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND	20

CAD (KiCad official)

Symbol: LTM4625EY#PBF
Footprint: Package_BGA:BGA-25_6.35x6.35mm_Layout5x5_P1.27mm
3D model: BGA-25 (KiCad packages3D, STEP)
3D model files: ltm4625ey-pbf-etched.step / ltm4625ey-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltm4625ey-pbf.step / ltm4625ey-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (26 pp, sha256 85df67ba0803249b, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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