component
LTM4624IY#PBF
Public Made by Adomby adom
Analog Devices Power Modules, BGA-25(6.2x6.2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
LTM4624IY#PBF
Analog Devices · Power Modules · BGA-25(6.2x6.2)
LTM4624IY#PBF from Analog Devices, in a BGA-25(6.2x6.2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | COMP | passive | Current control threshold and error amplifier compensation point; its normal range is 0.3V to 1.8V, and COMP pins are tied together for parallel operation. |
| A2 | TRACK/SS | input | Output tracking and soft-start input; a voltage below 0.6V servos FB to the TRACK/SS voltage, above 0.6V the internal reference resumes control, and an internal 2.5µA pull-up from INTVCC makes a capacitor here set soft-start. |
| A3 | RUN | input | Run control input that enables the regulator when tied above 1.25V and shuts it down when pulled below 1.1V; do not leave floating. |
| A4 | FREQ | input | Frequency pin where the switching frequency is set internally to 1MHz; an external resistor to SGND increases frequency and a resistor to INTVCC reduces it. |
| A5 | NC | unconnected | No connect pin, not connected internally; float or ground it. |
| B1 | FB | input | Negative input of the error amplifier, internally connected to VOUT through a 60.4k precision resistor, with output voltage programmed by an additional resistor between FB and SGND. |
| B2 | NC | unconnected | No connect pin, not connected internally; float or ground it. |
| B3 | GND | power_in | Power ground pin for both input and output returns. |
| B4 | SGND | power_in | Signal ground connection that must be tied to GND with minimum distance, and to which the FREQ, COMP, MODE, TRACK/SS and FB components connect as needed. |
| B5 | NC | unconnected | No connect pin, not connected internally; float or ground it. |
| C1 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| C2 | PGOOD | output | Open-drain power good output that is pulled to ground when the FB voltage is not within ±10% of the internal 0.6V reference. |
| C3 | GND | power_in | Power ground pin for both input and output returns. |
| C4 | MODE | input | Operation mode select; tie to INTVCC to force continuous synchronous operation at all loads, or to SGND for discontinuous mode at light loads; do not leave floating. |
| C5 | SVIN | power_in | Signal VIN that is the filtered input to the on-chip 3.3V regulator; connect to an external supply of at least 4V that must also be greater than VOUT, normally tied to VIN. |
| D1 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| D2 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| D3 | GND | power_in | Power ground pin for both input and output returns. |
| D4 | GND | power_in | Power ground pin for both input and output returns. |
| D5 | VIN | power_in | Power input pin; apply the input voltage between VIN and GND pins and place input decoupling capacitance directly between VIN and GND pins. |
| E1 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| E2 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| E3 | GND | power_in | Power ground pin for both input and output returns. |
| E4 | INTVCC | power_out | Internal 3.3V regulator output that powers the internal power drivers and control circuits and is internally decoupled to GND with a 1µF low ESR ceramic capacitor. |
| E5 | VIN | power_in | Power input pin; apply the input voltage between VIN and GND pins and place input decoupling capacitance directly between VIN and GND pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | BGA-25(6.2x6.2) |
| Category | Power Management ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input DC Voltage | VIN | 4 | 14 | V | SVIN = VIN | 2 | |
| Output Voltage Range | VOUT(RANGE) | 0.6 | 5.5 | V | 2 | ||
| Output Voltage, Total Variation with Line and Load | VOUT(DC) | 1.47 | 1.5 | 1.53 | V | CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k, MODE = INTVCC, VIN = 4V to 14V, IOUT = 0A to 4A (Note 3); -40°C to 125°C | 2 |
| RUN Pin On Threshold | VRUN | 1.1 | 1.2 | 1.3 | V | VRUN Rising | 2 |
| Line Regulation Accuracy | ΔVOUT (Line)/VOUT | 0.04 | 0.15 | %/V | VOUT = 1.5V, VIN = 4V to 14V, IOUT = 0A | 3 | |
| Load Regulation Accuracy | ΔVOUT (Load)/VOUT | 1 | 1.5 | % | VOUT = 1.5V, IOUT = 0A to 4A | 3 | |
| Output Continuous Current Range | IOUT(DC) | 0 | 4 | A | VIN = 12V, VOUT = 1.5V | 2 | |
| Output Current Limit | IOUTPK | 5 | 7 | A | VIN = 12V, VOUT = 1.5V | 3 | |
| Voltage at FB Pin | VFB | 0.594 | 0.6 | 0.606 | V | IOUT = 0A, VOUT = 1.5V | 3 |
| Voltage at FB Pin | VFB | 0.591 | 0.6 | 0.609 | V | IOUT = 0A, VOUT = 1.5V, -40°C to 125°C | 3 |
| Current at FB Pin | IFB | -30 | 30 | nA | Note 4 | 3 | |
| Resistor Between VOUT and FB Pins | RFBHI | 60.05 | 60.4 | 60.75 | kΩ | 3 | |
| Track Pin Soft-Start Pull-Up Current | ITRACK/SS | 2.5 | 4 | µA | TRACK/SS = 0V | 3 | |
| VIN Undervoltage Lockout | VIN(UVLO) | 2.4 | 2.6 | 2.8 | V | VIN Falling | 3 |
| PGOOD Trip Level, VFB Ramping Negative | VPGOOD | -13 | -10 | -7 | % | VFB with respect to set output; VFB ramping negative | 3 |
| PGOOD Trip Level, VFB Ramping Positive | VPGOOD | 7 | 10 | 13 | % | VFB with respect to set output; VFB ramping positive | 3 |
| PGOOD Voltage Low | VPGL | 0.02 | 0.1 | V | IPGOOD = 1mA | 3 | |
| Internal VCC Voltage | VINTVCC | 3.2 | 3.3 | 3.4 | V | SVIN = 4V to 14V | 3 |
| Input Voltage (VIN, SVIN) | VIN, SVIN | -0.3 | 15 | V | 2 | ||
| Output Voltage | VOUT | -0.3 | V | Note 4; upper limit printed as SVIN or 6V | 2 | ||
| RUN Pin Voltage | RUN | -0.3 | V | Upper limit printed as 15VIN | 2 | ||
| INTVCC Voltage | INTVCC | -0.3 | 3.6 | V | 2 | ||
| Digital Pin Voltage (PGOOD, MODE, TRACK/SS, FREQ) | PGOOD, MODE, TRACK/SS, FREQ | -0.3 | V | Upper limit printed as INTVCC | 2 | ||
| Feedback Pin Voltage (COMP, FB) | COMP, FB | -0.3 | V | Note 4; upper limit printed as INTVCC | 2 | ||
| Internal Operating Junction Temperature Range | -40 | 125 | °C | Notes 2, 5 | 2 | ||
| Storage Temperature Range | -55 | 125 | °C | 2 | |||
| Peak Solder Reflow Body Temperature | 245 | °C | Note 1 | 2 | |||
| Junction-to-Ambient Thermal Resistance | θJA | 22 | °C/W | Derived from 95mm × 76mm PCB with 4 layers; JESD 51-12 | 2 | ||
| Junction-to-Case (Top) Thermal Resistance | θJCtop | 17 | °C/W | JESD 51-12 | 2 | ||
| Junction-to-Case (Bottom) Thermal Resistance | θJCbottom | 11 | °C/W | JESD 51-12 | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND | 20 |
CAD (KiCad official)
- Symbol:
LTM4624IY#PBF - Footprint:
Package_BGA:BGA-25_6.35x6.35mm_Layout5x5_P1.27mm - 3D model: BGA-25(6.2x6.2) (KiCad packages3D, STEP)
- 3D model files:
ltm4624iy-pbf-etched.step/ltm4624iy-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltm4624iy-pbf.step/ltm4624iy-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
6cae4b5c5ec234fe, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTM4624IY#PBF
**Analog Devices** · Power Modules · BGA-25(6.2x6.2)
LTM4624IY#PBF from Analog Devices, in a BGA-25(6.2x6.2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | COMP | passive | Current control threshold and error amplifier compensation point; its normal range is 0.3V to 1.8V, and COMP pins are tied together for parallel operation. |
| A2 | TRACK/SS | input | Output tracking and soft-start input; a voltage below 0.6V servos FB to the TRACK/SS voltage, above 0.6V the internal reference resumes control, and an internal 2.5µA pull-up from INTVCC makes a capacitor here set soft-start. |
| A3 | RUN | input | Run control input that enables the regulator when tied above 1.25V and shuts it down when pulled below 1.1V; do not leave floating. |
| A4 | FREQ | input | Frequency pin where the switching frequency is set internally to 1MHz; an external resistor to SGND increases frequency and a resistor to INTVCC reduces it. |
| A5 | NC | unconnected | No connect pin, not connected internally; float or ground it. |
| B1 | FB | input | Negative input of the error amplifier, internally connected to VOUT through a 60.4k precision resistor, with output voltage programmed by an additional resistor between FB and SGND. |
| B2 | NC | unconnected | No connect pin, not connected internally; float or ground it. |
| B3 | GND | power_in | Power ground pin for both input and output returns. |
| B4 | SGND | power_in | Signal ground connection that must be tied to GND with minimum distance, and to which the FREQ, COMP, MODE, TRACK/SS and FB components connect as needed. |
| B5 | NC | unconnected | No connect pin, not connected internally; float or ground it. |
| C1 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| C2 | PGOOD | output | Open-drain power good output that is pulled to ground when the FB voltage is not within ±10% of the internal 0.6V reference. |
| C3 | GND | power_in | Power ground pin for both input and output returns. |
| C4 | MODE | input | Operation mode select; tie to INTVCC to force continuous synchronous operation at all loads, or to SGND for discontinuous mode at light loads; do not leave floating. |
| C5 | SVIN | power_in | Signal VIN that is the filtered input to the on-chip 3.3V regulator; connect to an external supply of at least 4V that must also be greater than VOUT, normally tied to VIN. |
| D1 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| D2 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| D3 | GND | power_in | Power ground pin for both input and output returns. |
| D4 | GND | power_in | Power ground pin for both input and output returns. |
| D5 | VIN | power_in | Power input pin; apply the input voltage between VIN and GND pins and place input decoupling capacitance directly between VIN and GND pins. |
| E1 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| E2 | VOUT | power_out | Power output pin; apply the load between VOUT and GND pins and place output decoupling capacitance directly between them. |
| E3 | GND | power_in | Power ground pin for both input and output returns. |
| E4 | INTVCC | power_out | Internal 3.3V regulator output that powers the internal power drivers and control circuits and is internally decoupled to GND with a 1µF low ESR ceramic capacitor. |
| E5 | VIN | power_in | Power input pin; apply the input voltage between VIN and GND pins and place input decoupling capacitance directly between VIN and GND pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | BGA-25(6.2x6.2) |
| Category | Power Management ICs |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input DC Voltage | VIN | 4 | | 14 | V | SVIN = VIN | 2 |
| Output Voltage Range | VOUT(RANGE) | 0.6 | | 5.5 | V | | 2 |
| Output Voltage, Total Variation with Line and Load | VOUT(DC) | 1.47 | 1.5 | 1.53 | V | CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k, MODE = INTVCC, VIN = 4V to 14V, IOUT = 0A to 4A (Note 3); -40°C to 125°C | 2 |
| RUN Pin On Threshold | VRUN | 1.1 | 1.2 | 1.3 | V | VRUN Rising | 2 |
| Line Regulation Accuracy | ΔVOUT (Line)/VOUT | | 0.04 | 0.15 | %/V | VOUT = 1.5V, VIN = 4V to 14V, IOUT = 0A | 3 |
| Load Regulation Accuracy | ΔVOUT (Load)/VOUT | | 1 | 1.5 | % | VOUT = 1.5V, IOUT = 0A to 4A | 3 |
| Output Continuous Current Range | IOUT(DC) | 0 | | 4 | A | VIN = 12V, VOUT = 1.5V | 2 |
| Output Current Limit | IOUTPK | 5 | | 7 | A | VIN = 12V, VOUT = 1.5V | 3 |
| Voltage at FB Pin | VFB | 0.594 | 0.6 | 0.606 | V | IOUT = 0A, VOUT = 1.5V | 3 |
| Voltage at FB Pin | VFB | 0.591 | 0.6 | 0.609 | V | IOUT = 0A, VOUT = 1.5V, -40°C to 125°C | 3 |
| Current at FB Pin | IFB | -30 | | 30 | nA | Note 4 | 3 |
| Resistor Between VOUT and FB Pins | RFBHI | 60.05 | 60.4 | 60.75 | kΩ | | 3 |
| Track Pin Soft-Start Pull-Up Current | ITRACK/SS | 2.5 | | 4 | µA | TRACK/SS = 0V | 3 |
| VIN Undervoltage Lockout | VIN(UVLO) | 2.4 | 2.6 | 2.8 | V | VIN Falling | 3 |
| PGOOD Trip Level, VFB Ramping Negative | VPGOOD | -13 | -10 | -7 | % | VFB with respect to set output; VFB ramping negative | 3 |
| PGOOD Trip Level, VFB Ramping Positive | VPGOOD | 7 | 10 | 13 | % | VFB with respect to set output; VFB ramping positive | 3 |
| PGOOD Voltage Low | VPGL | | 0.02 | 0.1 | V | IPGOOD = 1mA | 3 |
| Internal VCC Voltage | VINTVCC | 3.2 | 3.3 | 3.4 | V | SVIN = 4V to 14V | 3 |
| Input Voltage (VIN, SVIN) | VIN, SVIN | -0.3 | | 15 | V | | 2 |
| Output Voltage | VOUT | -0.3 | | | V | Note 4; upper limit printed as SVIN or 6V | 2 |
| RUN Pin Voltage | RUN | -0.3 | | | V | Upper limit printed as 15VIN | 2 |
| INTVCC Voltage | INTVCC | -0.3 | | 3.6 | V | | 2 |
| Digital Pin Voltage (PGOOD, MODE, TRACK/SS, FREQ) | PGOOD, MODE, TRACK/SS, FREQ | -0.3 | | | V | Upper limit printed as INTVCC | 2 |
| Feedback Pin Voltage (COMP, FB) | COMP, FB | -0.3 | | | V | Note 4; upper limit printed as INTVCC | 2 |
| Internal Operating Junction Temperature Range | | -40 | | 125 | °C | Notes 2, 5 | 2 |
| Storage Temperature Range | | -55 | | 125 | °C | | 2 |
| Peak Solder Reflow Body Temperature | | | | 245 | °C | Note 1 | 2 |
| Junction-to-Ambient Thermal Resistance | θJA | | 22 | | °C/W | Derived from 95mm × 76mm PCB with 4 layers; JESD 51-12 | 2 |
| Junction-to-Case (Top) Thermal Resistance | θJCtop | | 17 | | °C/W | JESD 51-12 | 2 |
| Junction-to-Case (Bottom) Thermal Resistance | θJCbottom | | 11 | | °C/W | JESD 51-12 | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND | 20 |
## CAD (KiCad official)
- Symbol: `LTM4624IY#PBF`
- Footprint: `Package_BGA:BGA-25_6.35x6.35mm_Layout5x5_P1.27mm`
- 3D model: BGA-25(6.2x6.2) (KiCad packages3D, STEP)
- 3D model files: `ltm4624iy-pbf-etched.step` / `ltm4624iy-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltm4624iy-pbf.step` / `ltm4624iy-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/4624fd.pdf) (26 pp, sha256 `6cae4b5c5ec234fe`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ltm4624iy-pbf-datasheet.pdf)