component

LTL431ATSLT1G

Public Made by Adom

by adom

LRC Voltage Reference, SOT-23. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ltl431atslt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ltl431atslt1g-etched.fit.json ltl431atslt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ltl431atslt1g-etched.glb ltl431atslt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ltl431atslt1g-etched.step ltl431atslt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ltl431atslt1g.glb Publish 0.1.0 · Ray
ltl431atslt1g.kicad_mod Publish 0.1.0 · Ray
ltl431atslt1g.kicad_sym Publish 0.1.0 · Ray
ltl431atslt1g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ltl431atslt1g.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json ltl431atslt1g: specified limits as data (metadata.characteristics, 10 rows from the datasheet) · Ray
README.md ltl431atslt1g: specified limits as data (metadata.characteristics, 10 rows from the datasheet) · Ray

LTL431ATSLT1G

LRC · Voltage Reference · SOT-23

LTL431ATSLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CATHODE passive Cathode (K) terminal of the shunt regulator. Sinks current (typ 1-100 mA, absolute max -100 to +150 mA) to regulate the cathode-to-anode voltage. Cathode voltage may be set from Vref (~2.5V) up to 36V. Dynamic impedance ~0.2 Ω.
2 REF input Reference (R) input pin. Internally compared against the 2.5V bandgap reference; the device regulates so that this pin sits at Vref (typ 2.495-2.50 V). Typical reference input current ~1 µA (max 2 µA). Connect to the R1/R2 divider from cathode to set output voltage: VKA = Vref x (1 + R1/R2) + Iref x R1.
3 ANODE passive Anode (A) terminal, typically tied to circuit ground / return. Return path for the cathode sink current and the internal reference amplifier.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • LTL431ATSLT1G
  • LTL431BTSLT1G
  • LTL431APTSLT1G
  • LTL431BPTSLT1G

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reference Input Voltage (1% grade, Reference Input Voltage 2 table) Vref 2.47 2.495 2.52 V VKA=VREF, IKA=10mA 2
Deviation of reference input voltage over temperature ΔVref 4.5 25 mV VKA=VREF, IKA=10mA, TMIN≤TA≤TMAX 2
Ratio of change in reference input voltage to change in cathode voltage (ΔVKA=10V~VREF) ΔVref/ΔVKA -1 -2.7 mV/V IKA=10mA, ΔVKA=10V~VREF 2
Ratio of change in reference input voltage to change in cathode voltage (ΔVKA=36V~10V) ΔVref/ΔVKA -0.5 -2 mV/V IKA=10mA, ΔVKA=36V~10V 2
Reference input current Iref 1 2 μA IKA=10mA, R1=10kΩ, R2=∞ 2
Deviation of reference input current over full temperature range ΔIref/ΔT 0.2 0.4 μA IKA=10mA, R1=10kΩ, R2=∞, TA=full temperature range 2
Minimum cathode current for regulation IKA(min) 0.3 0.5 mA VKA=VREF 2
Off-state cathode current IKA(OFF) 0.05 0.5 μA VKA=36V, VREF=0 2
Dynamic impedance ZKA 0.15 0.5 Ω VKA=VREF, IKA=1 to 100mA, f≤1.0kHz 2
Operating ambient temperature range Topr -40 125 °C Classification table temperature range for all listed grades 2

CAD (KiCad official)

  • Symbol: LTL431ATSLT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ltl431atslt1g-etched.step / ltl431atslt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltl431atslt1g.step / ltl431atslt1g.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ltl431atslt1g.step 59 KB You want the bare part, or you mark your own boards.
ltl431atslt1g-etched.step 1.6 MB You want the part with LTL431ATSLT1G already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 421 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (5 pp, sha256 a9ab6fd3d1d0d015, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF