component
LTL431ATSLT1G
Public Made by Adomby adom
LRC Voltage Reference, SOT-23. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C2912066). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+25−5
ltl431atslt1g.lbr+20−2@@ -57,6 +57,18 @@ <smd name="1" x="-0.9375" y="0.9500" dx="1.4750" dy="0.6000" layer="1"/> <smd name="2" x="-0.9375" y="-0.9500" dx="1.4750" dy="0.6000" layer="1"/> <smd name="3" x="0.9375" y="-0.0000" dx="1.4750" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.3000" y="0.3800"/>+ <vertex x="-1.0600" y="0.0500"/>+ <vertex x="-1.5400" y="0.0500"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.3250" y="1.4500"/>+ <vertex x="0.6500" y="1.4500"/>+ <vertex x="0.6500" y="-1.4500"/>+ <vertex x="-0.6500" y="-1.4500"/>+ <vertex x="-0.6500" y="1.1250"/>+ </polygon> <wire x1="-0.7600" y1="1.5600" x2="0.7600" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.7600" y1="1.5100" x2="-0.7600" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.7600" y1="-0.3900" x2="-0.7600" y2="0.3900" width="0.1200" layer="21"/>@@ -66,7 +78,7 @@ <wire x1="0.7600" y1="-1.5600" x2="-0.7600" y2="-1.5600" width="0.1200" layer="21"/> <text x="0" y="2.288" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-2.288" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.3000" y="0.3800"/><vertex x="-1.0600" y="0.0500"/><vertex x="-1.5400" y="0.0500"/></polygon></package>+</package> </packages> <symbols> <symbol name="LTL431ATSLT1G">@@ -94,7 +106,13 @@ <connect gate="G$1" pin="REF" pad="2"/> <connect gate="G$1" pin="ANODE" pad="3"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="LTL431ATSLT1G" constant="no"/>+ <attribute name="MANUFACTURER" value="LRC" constant="no"/>+ <attribute name="LCSC_PN" value="C2912066" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+5−3@@ -26,19 +26,21 @@ "model_3d_step": "ltl431atslt1g.step", "lbr": "ltl431atslt1g.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C2912066"+ }, "pins": [ { "number": "1", "name": "CATHODE", "type": "passive",- "description": "Cathode (K) terminal of the shunt regulator. Sinks current (typ 1-100 mA, absolute max -100 to +150 mA) to regulate the cathode-to-anode voltage. Cathode voltage may be set from Vref (~2.5V) up to 36V. Dynamic impedance ~0.2 Ω."+ "description": "Cathode (K) terminal of the shunt regulator. Sinks current (typ 1-100 mA, absolute max -100 to +150 mA) to regulate the cathode-to-anode voltage. Cathode voltage may be set from Vref (~2.5V) up to 36V. Dynamic impedance ~0.2 \u03a9." }, { "number": "2", "name": "REF", "type": "input",- "description": "Reference (R) input pin. Internally compared against the 2.5V bandgap reference; the device regulates so that this pin sits at Vref (typ 2.495-2.50 V). Typical reference input current ~1 µA (max 2 µA). Connect to the R1/R2 divider from cathode to set output voltage: VKA = Vref x (1 + R1/R2) + Iref x R1."+ "description": "Reference (R) input pin. Internally compared against the 2.5V bandgap reference; the device regulates so that this pin sits at Vref (typ 2.495-2.50 V). Typical reference input current ~1 \u00b5A (max 2 \u00b5A). Connect to the R1/R2 divider from cathode to set output voltage: VKA = Vref x (1 + R1/R2) + Iref x R1." }, { "number": "3",