component

LTL431ATLT1G

Public Made by Adom

by adom

LRC Voltage Reference, SOT-23. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ltl431atlt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ltl431atlt1g-etched.fit.json ltl431atlt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ltl431atlt1g-etched.glb ltl431atlt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ltl431atlt1g-etched.step ltl431atlt1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ltl431atlt1g.glb Publish 0.1.0 · Ray
ltl431atlt1g.kicad_mod Publish 0.1.0 · Ray
ltl431atlt1g.kicad_sym Publish 0.1.0 · Ray
ltl431atlt1g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ltl431atlt1g.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json ltl431atlt1g: specified limits as data (metadata.characteristics, 2 rows from the datasheet) · Ray
README.md ltl431atlt1g: specified limits as data (metadata.characteristics, 2 rows from the datasheet) · Ray

LTL431ATLT1G

LRC · Voltage Reference · SOT-23

LTL431ATLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CATHODE passive Cathode (K) terminal. Sinks the regulated current when VKA >= Vref (~2.5V). Absolute maximum VKA = 36V; cathode current range -100 mA to +150 mA continuous; minimum cathode current for regulation IKA(min) typ 0.45 mA, max 1.0 mA. Dynamic impedance typ 0.15 Ω at f <= 1 kHz.
2 REF input Reference (R) input. High-impedance sense input to the internal error amplifier compared against the internal 2.5V bandgap reference (Vref typ 2.495-2.50V). Reference input current Iref typ 1.5 µA (max 4 µA) with R1 = 10 kΩ. Output is programmed via VO = (1 + R1/R2) * Vref.
3 ANODE passive Anode (A) terminal. Common/ground return for the reference; internal error amplifier and output transistor emitter reference. Typically tied to circuit ground in shunt-regulator configurations.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • LTL431ATLT1GALT1G
  • LTL431ATLT1GBLT1G
  • LTL431ATLT1GAPLT1G
  • LTL431ATLT1GBPLT1G
  • LTL431ATLT1G
  • LTL431ATLT1GBTLT1G
  • LTL431ATLT1GAPTLT1G
  • LTL431ATLT1GBPTLT1G

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reference input voltage (rank A, 0.5%, -40 to +125 °C classification) VREF 2.482 2.507 V Classification table; Vref range for LTL431ATLT1 family. Row-to-variant assignment uncertain, see review_required 2
Operating ambient temperature range TOPR 0 70 °C Absolute maximum table note: operating temperature range applies unless otherwise specified. Printed range is 0 to +70 °C; the T-suffix classification lists -40 to +125 °C, see review_required 2

CAD (KiCad official)

  • Symbol: LTL431ATLT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ltl431atlt1g-etched.step / ltl431atlt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltl431atlt1g.step / ltl431atlt1g.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ltl431atlt1g.step 59 KB You want the bare part, or you mark your own boards.
ltl431atlt1g-etched.step 1.3 MB You want the part with LTL431ATLT1G already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 365 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (5 pp, sha256 f72860759bbf8e8d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF