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LTC8552XF8

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Linearin Precision OpAmps, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LTC8552XF8

Linearin · Precision OpAmps · DFN-8-EP(2x2)

LTC8552XF8 from Linearin, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUTA output Amplifier A output (rail-to-rail), safe for capacitive loads up to 500pF.
2 -INA input Inverting input of amplifier A, common-mode range VS- − 0.1 V to VS+ + 0.1 V.
3 +INA input Non-inverting input of amplifier A, common-mode range VS- − 0.1 V to VS+ + 0.1 V.
4 -VS power_in Negative (lowest) power supply; total supply VS+ to VS- is 2.0 V to 5.5 V specified, 10.0 V absolute maximum.
5 +INB input Non-inverting input of amplifier B, common-mode range VS- − 0.1 V to VS+ + 0.1 V.
6 -INB input Inverting input of amplifier B, common-mode range VS- − 0.1 V to VS+ + 0.1 V.
7 OUTB output Amplifier B output (rail-to-rail), safe for capacitive loads up to 500pF.
8 +VS power_in Positive (highest) power supply; 2.0 V to 5.5 V specified over -40 to +125 °C (1.8 V at 0 to +70 °C), 10.0 V absolute maximum.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Linearin
Package DFN-8-EP(2x2)
Category Operational Amplifier/Comparator
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VS+ to VS- 10 V 2
Signal input terminals current -20 20 mA 2
Storage temperature range Tstg -65 150 ℃ 2
Junction temperature TJ 150 ℃ 2
Lead temperature range (soldering 10 sec) 260 ℃ Soldering 10 sec 2
Electrostatic discharge voltage, human body model (HBM) -5000 5000 V Per MIL-STD-883J / Method 3015.9 2
Electrostatic discharge voltage, charged device model (CDM) -2000 2000 V Per ESDA/JEDEC JS-002-2014 2
Electrostatic discharge voltage, machine model (MM) -250 250 V Per JESD22-A115C 2
Input offset voltage VOS -8 2 8 μV 3
Offset voltage drift VOS TC -40 5 40 nV/℃ TA = −40 to +125 ℃ 3
Power supply rejection ratio PSRR 112 126 dB VS = 2.0 to 5.5 V, VCM < VS+ − 2V 3
Power supply rejection ratio over temperature PSRR 106 dB TA = −40 to +125 ℃ 3
Input bias current IB -70 70 pA 3
Input bias current at TA = +85 ℃ IB -150 150 pA TA = +85 ℃ 3
Input bias current at TA = +125 ℃ IB -700 700 pA TA = +125 ℃ 3
Input offset current IOS -100 100 pA 3
Common-mode rejection ratio CMRR 112 130 dB VS = 5.5 V, VCM = −0.1 to 5.5 V 3
Common-mode rejection ratio over temperature CMRR 106 dB VCM = 0 to 5.3 V, TA = −40 to +125 ℃ 3
Common-mode rejection ratio at 2.0 V supply CMRR 102 122 dB VS = 2.0 V, VCM = −0.1 to 2.0 V 3
Common-mode rejection ratio at 2.0 V supply over temperature CMRR 96 dB VCM = 0 to 1.8 V, TA = −40 to +125 ℃ 3
Open-loop voltage gain AVOL 112 132 dB RL = 20 kΩ, VO = 0.05 to 3.5 V 3
Open-loop voltage gain over temperature AVOL 106 dB TA = −40 to +125 ℃ 3
Open-loop voltage gain, RL = 2 kΩ AVOL 101 120 dB RL = 2 kΩ, VO = 0.15 to 3.5 V 3
Open-loop voltage gain, RL = 2 kΩ, over temperature AVOL 95 dB TA = −40 to +125 ℃ 3
Operating supply voltage VS 1.8 5.5 V TA = 0 to +70 ℃ 4
Operating supply voltage over extended temperature VS 2 5.5 V TA = −40 to +125 ℃ 4
Quiescent current (per amplifier) IQ 80 125 190 μA 4
Operating temperature range TA -40 125 ℃ 4
Input offset voltage drift typical marker not separately printed; input voltage noise (0.01 to 1 Hz) Vn 0.1 μVP-P f = 0.01 to 1 Hz 3
Input voltage noise (0.1 to 10 Hz) Vn 0.45 μVP-P f = 0.1 to 10 Hz 3
Input voltage noise density en 15 nV/√Hz f = 10 kHz 3
Input voltage noise density en 19 nV/√Hz f = 1 kHz 3
Input current noise density In 10 fA/√Hz f = 1 kHz 3
Input resistance RIN 100 GΩ 3
Input capacitance, differential CIN 2 pF Differential 3
Input capacitance, common mode CIN 3.5 pF Common mode 3
Gain bandwidth product GBW 1.5 MHz f = 1 kHz 3
Slew rate SR 1.2 V/μs G = +1, CL = 100 pF, VO = 1.5 to 3.5 V 3
Settling time to 0.1% tS 1.2 μs To 0.1%, G = +1, 1V step 3
Settling time to 0.01% tS 1.5 μs To 0.01%, G = +1, 1V step 3
Overload recovery time tOR 35 μs To 0.1%, VIN * Gain > VS 3
Open-loop output impedance ZOUT 2 kΩ f = 350 kHz, IO = 0 4
Short-circuit source current ISC 40 mA Source current through 10Ω 4
Short-circuit sink current ISC 50 mA Sink current through 10Ω 4
Package thermal resistance, junction to ambient (DFN2x2-8L) θJA 80 ℃/W DFN2x2-8L 4

CAD (KiCad official)

  • Symbol: LTC8552XF8
  • Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
  • 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: ltc8552xf8-etched.step / ltc8552xf8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc8552xf8.step / ltc8552xf8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Linearin datasheet (22 pp, sha256 75ef8d8e529a155f, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF