component
LTC8542XF8
Public Made by Adomby adom
Linearin Operational Amplifier, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLTC8542XF8
Linearin · Operational Amplifier · DFN-8-EP(2x2)
LTC8542XF8 from Linearin, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output. |
| 2 | -INA | input | Inverting input of amplifier A; voltage range can go from (VS- - 0.1V) to (VS+ + 0.1V). |
| 3 | +INA | input | Non-inverting input of amplifier A, with the same voltage range as -IN ((VS- - 0.1V) to (VS+ + 0.1V)). |
| 4 | -VS | power_in | Negative power supply, normally tied to ground; VS+ to VS- must be 2.0V to 5.5V, and bypass with 0.1μF close to the part if not grounded. |
| 5 | +INB | input | Non-inverting input of amplifier B, with the same voltage range as -IN ((VS- - 0.1V) to (VS+ + 0.1V)). |
| 6 | -INB | input | Inverting input of amplifier B; voltage range can go from (VS- - 0.1V) to (VS+ + 0.1V). |
| 7 | OUTB | output | Amplifier B output. |
| 8 | +VS | power_in | Positive power supply, 2.0V to 5.5V, with a 0.1μF bypass capacitor as close to the part as possible. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin |
| Package | DFN-8-EP(2x2) |
| Category | Amplifiers |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage | VOS | -2.5 | 0.5 | 2.5 | mV | VS=5.0V, TA=+25℃ (typ ±0.5) | 3 |
| Common-mode rejection ratio | CMRR | 80 | 97 | dB | VCM = 0.05V to 3.5V | 3 | |
| Common-mode rejection ratio over temperature | CMRR | 70 | dB | VCM = 0.05V to 3.5V, over Temperature | 3 | ||
| Common-mode rejection ratio | CMRR | 70 | 82 | dB | VCM = VS- -0.1 to VS+ +0.1 V | 3 | |
| Common-mode rejection ratio over temperature | CMRR | 66 | dB | VCM = VS- -0.1 to VS+ +0.1 V, over Temperature | 3 | ||
| Open-loop voltage gain | AVOL | 102 | 116 | dB | RL = 10kΩ, VO = 0.05 to 3.5 V | 3 | |
| Open-loop voltage gain over temperature | AVOL | 90 | dB | RL = 10kΩ, VO = 0.05 to 3.5 V, over Temperature | 3 | ||
| Open-loop voltage gain | AVOL | 93 | 108 | dB | RL = 2kΩ, VO = 0.15 to 3.5 V | 3 | |
| Open-loop voltage gain over temperature | AVOL | 82 | dB | RL = 2kΩ, VO = 0.15 to 3.5 V, over Temperature | 3 | ||
| Common-mode voltage range | VCM | -0.1 | 0.1 | V | VS- -0.1 min; VS+ +0.1 max (relative to supply rails) | 3 | |
| Power supply rejection ratio | PSRR | 82 | 102 | dB | VS = 2.0V to 5.5V, VCM < VS+ − 2V | 4 | |
| Power supply rejection ratio over temperature | PSRR | 75 | dB | over Temperature | 4 | ||
| Quiescent current (per amplifier) | IQ | 70 | 120 | μA | 4 | ||
| Quiescent current (per amplifier) over temperature | IQ | 150 | μA | over Temperature | 4 | ||
| Operating supply voltage | VS | 2 | 5.5 | V | 4 | ||
| Operating temperature range | TA | -40 | 125 | ℃ | 4 | ||
| Supply voltage, VS+ to VS- | 10 | V | 2 | ||||
| Storage temperature range | -65 | 150 | ℃ | 2 | |||
| Junction temperature | 160 | ℃ | 2 | ||||
| Lead temperature (soldering 10 sec) | 260 | ℃ | 2 | ||||
| ESD HBM | -4000 | 4000 | V | 2 | |||
| ESD CDM | -2000 | 2000 | V | 2 | |||
| ESD MM | -400 | 400 | V | 2 | |||
| Package thermal resistance DFN2x2-8L | θJA | 80 | ℃/W | DFN2x2-8L | 4 | ||
| Offset voltage drift over temperature | VOS TC | 2 | μV/℃ | 3 | |||
| Input bias current | IB | 150 | pA | TA = +85 ℃ | 3 | ||
| Input bias current | IB | 500 | pA | TA = +125 ℃ | 3 | ||
| Input offset current | IOS | 1 | pA | 3 | |||
| Gain bandwidth product | GBW | 1.3 | MHz | f = 1kHz | 3 | ||
| Slew rate | SR | 1.1 | V/μs | G = +1, CL = 100pF, VO = 1.5V to 3.5V | 3 | ||
| Phase margin | ΦM | 66 | ° | CL = 100pF | 3 | ||
| Input resistance | RIN | 100 | GΩ | 3 |
CAD (KiCad official)
- Symbol:
LTC8542XF8 - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
ltc8542xf8-etched.step/ltc8542xf8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc8542xf8.step/ltc8542xf8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Linearin datasheet (19 pp, sha256
54e840e21b5ec3d4, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).