component
LTC7878AUH#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLTC7878AUH#TRPBF
Analog Devices · DC-DC Converters · QFN-32(5x5)
LTC7878AUH#TRPBF from Analog Devices, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BG1 | output | Bottom gate driver output that drives the bottom N-channel MOSFET gate between PGND and DRVCC. |
| 2 | VIN | power_in | Main IC supply input to the internal LDO, to be bypassed to PGND with 0.1µF to 1µF placed close to the pin. |
| 3 | DRVCC | power_out | Gate driver LDO output regulated to 7V from VIN or EXTVCC, to be bypassed to PGND with a minimum of 4.7µF low-ESR tantalum or ceramic capacitor. |
| 4 | EXTVCC | power_in | External power input to an internal LDO connected to DRVCC; when its voltage is greater than 8V and lower than the VIN voltage, it bypasses the VIN-powered LDO, and it is bypassed to PGND with 0.1µF to 1µF. |
| 5 | INTVCC | power_out | Internal 5V regulator output that powers the control circuits, to be bypassed to SGND with a minimum of 4.7µF low-ESR capacitor. |
| 6 | RUN | input | Enable control input where a voltage above 1.22V turns on the IC, with a 2µA pull-up that increases to 6µA once RUN rises above the threshold. |
| 7 | PGND | power_in | Power ground that must be connected closely to the bottom MOSFET sources and the negative terminals of the VIN, DRVCC and EXTVCC bypass capacitors. |
| 8 | BG2 | output | Bottom gate driver output that drives the bottom N-channel MOSFET gate between PGND and DRVCC. |
| 9 | TG2 | output | Top gate driver output of a floating driver with a voltage swing equal to DRVCC superimposed on the SW2 switching node voltage. |
| 10 | BOOST2 | power_out | Bootstrapped supply for the top-side floating driver 2, swinging from DRVCC to (VOUT + DRVCC), with a bootstrap capacitor to SW2 and a Schottky diode to DRVCC. |
| 11 | SW2 | passive | Switch node connection normally tied to the inductor, swinging from a Schottky diode drop below ground up to VOUT, with a 0.1µF to 1µF bootstrap capacitor to BOOST2. |
| 12 | PGOOD | output | Open-drain power good output pulled to ground when the regulated output exceeds the ±10% window after the internal 30µs power bad mask timer expires. |
| 13 | SS | passive | Soft-start pin with a 2.5µA pull-up whose capacitor to ground sets the output voltage ramp rate. |
| 14 | ITHB | passive | Fast transient current control threshold pin that may be configured with a resistor to ITH, and must not be left floating (short to ITH if unused). |
| 15 | ITH | passive | Current control threshold and error amplifier compensation point, with the compensation network connected from ITH to SGND. |
| 16 | VFB | input | Output voltage sense input to the error amplifier noninverting input, receiving the remotely sensed feedback from an external resistor divider across the output. |
| 17 | MODE/ILIM | input | Tying to GND or INTVCC enables forced continuous mode, otherwise pulse-skipping mode is used, and a voltage below INTVCC/2 selects the low current limit while above INTVCC/2 selects the high current limit. |
| 18 | PHASMD | input | Phase mode program pin that sets the CLKOUT phase shift: tie to SGND for 180°, float for 120°, or tie to INTVCC for 90°. |
| 19 | FREQ | passive | Frequency set pin where a resistor to SGND sets the switching frequency, with the pin sourcing 10µA. |
| 20 | CLKOUT | output | Clock output used to synchronize the switching frequency of multiple LTC7878 ICs in parallel operation, swinging from INTVCC to ground. |
| 21 | SYNC | input | Switching frequency synchronization input that locks to an external clock between 100kHz and 600kHz, and uses the FREQ resistor setting when low, with a 500k internal resistor to ground. |
| 22 | SETCUR | passive | Average current regulation pin where a resistor to SGND sets the maximum average input or output current, with the pin sourcing 15µA. |
| 23 | CSP | input | Positive input of the internal rail-to-rail average current sense amplifier. |
| 24 | CSN | input | Negative input of the internal rail-to-rail average current sense amplifier. |
| 25 | VOUT | power_in | Floating driver bias pin in boost mode that supplies bias current for the BOOST1 to SW1 driver circuitry when VOUT is much higher than VIN. |
| 26 | NC | unconnected | No connect pin. |
| 27 | ISNSN | input | Negative input of the current sense comparator, normally connected to the DCR sensing network. |
| 28 | ISNSP | input | Positive input of the current sense comparator that must be Kelvin connected to the inductor on switching node SW1. |
| 29 | ISNSD | input | DC current sense comparator input that amplifies the DC portion of the sensed current, and is shorted locally to ISNSP if unused in large DCR applications. |
| 30 | SW1 | passive | Switch node connection normally tied to the inductor, swinging from a Schottky diode drop below ground up to VIN, with a 0.1µF to 1µF bootstrap capacitor to BOOST1. |
| 31 | BOOST1 | power_out | Bootstrapped supply for the top-side floating driver 1, swinging from DRVCC to (VIN + DRVCC), with a bootstrap capacitor to SW1 and a Schottky diode to DRVCC. |
| 32 | TG1 | output | Top gate driver output of a floating driver with a voltage swing equal to DRVCC superimposed on the SW1 switching node voltage. |
| 33 | SGND | power_in | Signal ground exposed pad that must be soldered to PCB ground for rated thermal performance, and to which all small-signal components (INTVCC, SS, ITH, VFB, FREQ, etc.) connect. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-32(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Bias Input Supply Operating Voltage Range | 5 | 70 | V | 3 | |||
| EXTVcc Auxiliary Bias Voltage Operating Range | 5 | 70 | V | 3 | |||
| VIN Supply Current (Shutdown Mode) | IQ | 70 | 100 | µA | VIN = 5V, RUN = 0V, EXTVCC = 0V | 3 | |
| VOUT Output Voltage Operating Range | 1 | 70 | V | 3 | |||
| Regulated Feedback Voltage | VFB | 0.99 | 1 | 1.01 | V | ITH, ITHB Voltage = 1.2V | 3 |
| VFB Pin Current | IVFB | -50 | -100 | nA | 3 | ||
| Reference Voltage Line Regulation | VREFLNREG | 0.01 | 0.2 | % | VIN = 12V to 72V | 3 | |
| Output Voltage Load Regulation | VLOADREG | 0.05 | 0.2 | % | Measure in Servo Loop, ITH = ITHB, ΔITH Voltage = 1.2V to 1.8V | 3 | |
| Output Voltage Load Regulation | VLOADREG | -0.05 | -0.2 | % | Measure in Servo Loop, ITH = ITHB, ΔITH Voltage = 1.2V to 0.6V | 3 | |
| DRVCC Undervoltage Lockout | UVLO_DRVCC | 3.9 | 4.3 | 4.5 | V | DRVCC Ramping Down | 3 |
| RUN Pin Threshold 1 (Shutdown to Standby) | VRUN | 0.3 | 0.57 | V | VRUN Rising | 3 | |
| RUN Pin Threshold 2 (Standby to On) | VRUN | 1.1 | 1.2 | 1.3 | V | VRUN Rising | 3 |
| Maximum Inductor Peak Current Sense Threshold | VSENSE(ILMAX) | 18 | 25 | 32 | mV | MODE/ILIM < INTVCC/2, ITH = ITHB = 2.1V, VISNSP, VISNSD = 25mV | 3 |
| Maximum Inductor Peak Current Sense Threshold | VSENSE(ILMAX) | 40 | 50 | 60 | mV | MODE/ILIM > INTVCC/2, ITH = ITHB = 2.1V, VISNSP, VISNSD = 50mV | 3 |
| Maximum Inductor Peak Current Sense Threshold | VSENSE(ILMAX) | 92 | 100 | 108 | mV | MODE/ILIM < INTVCC/2, ITH = ITHB = 2.1V, VISNSP = VISNSD | 3 |
| Maximum Inductor Peak Current Sense Threshold | VSENSE(ILMAX) | 190 | 200 | 210 | mV | MODE/ILIM > INTVCC/2, ITH = ITHB = 2.1V, VISNSP = VISNSD | 3 |
| ISNSD Pin Leakage Current | IISNSD | -0.1 | 0 | 0.1 | µA | 3 | |
| ISNSN Pin Leakage Current | IISNSN | -0.1 | 0 | 0.1 | µA | 3 | |
| CSP Pin Input Current | ICSP | 14 | 20 | µA | VCSP = VCSN > 5V, VCSP, VCSN = 50mV | 3 | |
| CSN Pin Input Current | ICSN | 14 | 20 | µA | VCSP = VCSN > 5V, VCSP, VCSN = 50mV | 3 | |
| CSP/CSN Pin Current Mismatch | ΔICS | -1 | 0.05 | 1 | µA | VCSP = 12V, VCSP, VCSN = 50mV | 3 |
| Maximum Average Current Limit | VMAX(IAVG) | 46.5 | 50 | 53 | mV | VCSP = 12V | 3 |
| SETCUR Pin Output Current | ISETCUR | 14 | 15 | 16 | µA | 3 | |
| DRVCC Regulation Voltage | VDRVCC | 6.8 | 7 | 7.2 | V | VIN = 12V, EXTVCC = 0V | 4 |
| DRVCC Voltage Load Regulation | VDRVCC_LREG | 1 | 2 | % | IDRVCC = 0mA to 55mA, VIN = 12V | 4 | |
| INTVCC Regulation Voltage | VINTVCC | 4.8 | 5 | 5.2 | V | 4 | |
| FREQ Pin Output Current | IFREQ | 9 | 10 | 11 | µA | 4 | |
| Synchronizable Frequency | fSW_SYNC | 100 | 600 | kHz | SYNC = External Clock | 4 | |
| SYNC Pin Input Threshold (SYNC Pin Rising) | VTH_SYNC | 1.2 | 2 | V | SYNC Pin Rising | 4 | |
| SYNC Pin Input Threshold (SYNC Pin Falling) | VTH_SYNC | 0.5 | 0.9 | V | SYNC Pin Falling | 4 | |
| Clock Output High Voltage | 4.8 | 5 | V | 4 | |||
| Clock Output Low Voltage | 0 | 0.2 | V | 4 | |||
| PGOOD Leakage Current | IPGOOD | -1 | 1 | µA | VPGOOD = 6V | 4 | |
| Input and Output Voltage | VIN, VOUT | -0.3 | 72 | V | 2 | ||
| Topside Driver Voltages (BOOST1, BOOST2) | -0.3 | 78 | V | 2 | |||
| Switch Voltages (SW1, SW2) | -5 | 72 | V | 2 | |||
| Boost-to-Switch Voltage (BOOST1, SW1, BOOST2, SW2) | -0.3 | 8 | V | 2 | |||
| Inductor Current Sense Voltages (ISNSP, ISNSN, ISNSD) | -5 | 72 | V | 2 | |||
| Input/Output Current Sense Voltages (CSP, CSN) | -0.3 | 72 | V | 2 | |||
| EXTVCC Voltage | -0.3 | 72 | V | 2 | |||
| RUN Voltage | -0.3 | 12 | V | 2 | |||
| PGOOD Voltage | -0.3 | 6 | V | 2 | |||
| ITH, ITHB, VFB Voltages | -0.3 | V | 2 | ||||
| PHASMD, SETCUR, SS Voltages | -0.3 | V | 2 | ||||
| FREQ, SYNC, CLKOUT Voltages | -0.3 | V | 2 | ||||
| MODE/ILIM Voltage | -0.3 | V | 2 | ||||
| DRVCC Peak Current | 100 | mA | 2 | ||||
| Operating Junction Temperature Range (LTC7878A) | TJ | -40 | 125 | °C | LTC7878A | 2 | |
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Maximum Junction Temperature | TJMAX | 125 | °C | 2 | |||
| Junction-to-Ambient Thermal Resistance | θJA | 34 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LTC7878AUH#TRPBF - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
ltc7878auh-trpbf-etched.step/ltc7878auh-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc7878auh-trpbf.step/ltc7878auh-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (29 pp, sha256
570c451c2e04a375, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).